lowlevel_init.S 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
  4. *
  5. * u-boot/board/r7780mp/lowlevel_init.S
  6. */
  7. #include <config.h>
  8. #include <asm/processor.h>
  9. #include <asm/macro.h>
  10. /*
  11. * Board specific low level init code, called _very_ early in the
  12. * startup sequence. Relocation to SDRAM has not happened yet, no
  13. * stack is available, bss section has not been initialised, etc.
  14. *
  15. * (Note: As no stack is available, no subroutines can be called...).
  16. */
  17. .global lowlevel_init
  18. .text
  19. .align 2
  20. lowlevel_init:
  21. write32 CCR_A, CCR_D /* Address of Cache Control Register */
  22. /* Instruction Cache Invalidate */
  23. write32 FRQCR_A, FRQCR_D /* Frequency control register */
  24. /* pin_multi_setting */
  25. write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
  26. write32 BBG_PMSR1_A, BBG_PMSR1_D
  27. write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
  28. write32 BBG_PMSR2_A, BBG_PMSR2_D
  29. write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
  30. write32 BBG_PMSR3_A, BBG_PMSR3_D
  31. write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
  32. write32 BBG_PMSR4_A, BBG_PMSR4_D
  33. write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
  34. write32 BBG_PMSRG_A, BBG_PMSRG_D
  35. /* cpg_setting */
  36. write32 FRQCR_A, FRQCR_D
  37. write32 DLLCSR_A, DLLCSR_D
  38. nop
  39. nop
  40. nop
  41. nop
  42. nop
  43. nop
  44. nop
  45. nop
  46. nop
  47. nop
  48. /* wait 200us */
  49. mov.l REPEAT0_R3, r3
  50. mov #0, r2
  51. repeat0:
  52. add #1, r2
  53. cmp/hs r3, r2
  54. bf repeat0
  55. nop
  56. /* bsc_setting */
  57. write32 MMSELR_A, MMSELR_D
  58. write32 BCR_A, BCR_D
  59. write32 CS0BCR_A, CS0BCR_D
  60. write32 CS1BCR_A, CS1BCR_D
  61. write32 CS2BCR_A, CS2BCR_D
  62. write32 CS4BCR_A, CS4BCR_D
  63. write32 CS5BCR_A, CS5BCR_D
  64. write32 CS6BCR_A, CS6BCR_D
  65. write32 CS0WCR_A, CS0WCR_D
  66. write32 CS1WCR_A, CS1WCR_D
  67. write32 CS2WCR_A, CS2WCR_D
  68. write32 CS4WCR_A, CS4WCR_D
  69. write32 CS5WCR_A, CS5WCR_D
  70. write32 CS6WCR_A, CS6WCR_D
  71. write32 CS5PCR_A, CS5PCR_D
  72. write32 CS6PCR_A, CS6PCR_D
  73. /* ddr_setting */
  74. /* wait 200us */
  75. mov.l REPEAT0_R3, r3
  76. mov #0, r2
  77. repeat1:
  78. add #1, r2
  79. cmp/hs r3, r2
  80. bf repeat1
  81. nop
  82. mov.l MIM_U_A, r0
  83. mov.l MIM_U_D, r1
  84. synco
  85. mov.l r1, @r0
  86. synco
  87. mov.l MIM_L_A, r0
  88. mov.l MIM_L_D0, r1
  89. synco
  90. mov.l r1, @r0
  91. synco
  92. mov.l STR_L_A, r0
  93. mov.l STR_L_D, r1
  94. synco
  95. mov.l r1, @r0
  96. synco
  97. mov.l SDR_L_A, r0
  98. mov.l SDR_L_D, r1
  99. synco
  100. mov.l r1, @r0
  101. synco
  102. nop
  103. nop
  104. nop
  105. nop
  106. mov.l SCR_L_A, r0
  107. mov.l SCR_L_D0, r1
  108. synco
  109. mov.l r1, @r0
  110. synco
  111. mov.l SCR_L_A, r0
  112. mov.l SCR_L_D1, r1
  113. synco
  114. mov.l r1, @r0
  115. synco
  116. nop
  117. nop
  118. nop
  119. mov.l EMRS_A, r0
  120. mov.l EMRS_D, r1
  121. synco
  122. mov.l r1, @r0
  123. synco
  124. nop
  125. nop
  126. nop
  127. mov.l MRS1_A, r0
  128. mov.l MRS1_D, r1
  129. synco
  130. mov.l r1, @r0
  131. synco
  132. nop
  133. nop
  134. nop
  135. mov.l SCR_L_A, r0
  136. mov.l SCR_L_D2, r1
  137. synco
  138. mov.l r1, @r0
  139. synco
  140. nop
  141. nop
  142. nop
  143. mov.l SCR_L_A, r0
  144. mov.l SCR_L_D3, r1
  145. synco
  146. mov.l r1, @r0
  147. synco
  148. nop
  149. nop
  150. nop
  151. mov.l SCR_L_A, r0
  152. mov.l SCR_L_D4, r1
  153. synco
  154. mov.l r1, @r0
  155. synco
  156. nop
  157. nop
  158. nop
  159. mov.l MRS2_A, r0
  160. mov.l MRS2_D, r1
  161. synco
  162. mov.l r1, @r0
  163. synco
  164. nop
  165. nop
  166. nop
  167. mov.l SCR_L_A, r0
  168. mov.l SCR_L_D5, r1
  169. synco
  170. mov.l r1, @r0
  171. synco
  172. /* wait 200us */
  173. mov.l REPEAT0_R1, r3
  174. mov #0, r2
  175. repeat2:
  176. add #1, r2
  177. cmp/hs r3, r2
  178. bf repeat2
  179. synco
  180. mov.l MIM_L_A, r0
  181. mov.l MIM_L_D1, r1
  182. synco
  183. mov.l r1, @r0
  184. synco
  185. rts
  186. nop
  187. .align 4
  188. RWTCSR_D_1: .word 0xA507
  189. RWTCSR_D_2: .word 0xA507
  190. RWTCNT_D: .word 0x5A00
  191. .align 2
  192. BBG_PMMR_A: .long 0xFF800010
  193. BBG_PMSR1_A: .long 0xFF800014
  194. BBG_PMSR2_A: .long 0xFF800018
  195. BBG_PMSR3_A: .long 0xFF80001C
  196. BBG_PMSR4_A: .long 0xFF800020
  197. BBG_PMSRG_A: .long 0xFF800024
  198. BBG_PMMR_D_PMSR1: .long 0xffffbffd
  199. BBG_PMSR1_D: .long 0x00004002
  200. BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
  201. BBG_PMSR2_D: .long 0x03de5800
  202. BBG_PMMR_D_PMSR3: .long 0xfffffff8
  203. BBG_PMSR3_D: .long 0x00000007
  204. BBG_PMMR_D_PMSR4: .long 0xdffdfff9
  205. BBG_PMSR4_D: .long 0x20020006
  206. BBG_PMMR_D_PMSRG: .long 0xffffffff
  207. BBG_PMSRG_D: .long 0x00000000
  208. FRQCR_A: .long FRQCR
  209. DLLCSR_A: .long 0xffc40010
  210. FRQCR_D: .long 0x40233035
  211. DLLCSR_D: .long 0x00000000
  212. /* for DDR-SDRAM */
  213. MIM_U_A: .long MIM_1
  214. MIM_L_A: .long MIM_2
  215. SCR_U_A: .long SCR_1
  216. SCR_L_A: .long SCR_2
  217. STR_U_A: .long STR_1
  218. STR_L_A: .long STR_2
  219. SDR_U_A: .long SDR_1
  220. SDR_L_A: .long SDR_2
  221. EMRS_A: .long 0xFEC02000
  222. MRS1_A: .long 0xFEC00B08
  223. MRS2_A: .long 0xFEC00308
  224. MIM_U_D: .long 0x00004000
  225. MIM_L_D0: .long 0x03e80009
  226. MIM_L_D1: .long 0x03e80209
  227. SCR_L_D0: .long 0x3
  228. SCR_L_D1: .long 0x2
  229. SCR_L_D2: .long 0x2
  230. SCR_L_D3: .long 0x4
  231. SCR_L_D4: .long 0x4
  232. SCR_L_D5: .long 0x0
  233. STR_L_D: .long 0x000f0000
  234. SDR_L_D: .long 0x00000400
  235. EMRS_D: .long 0x0
  236. MRS1_D: .long 0x0
  237. MRS2_D: .long 0x0
  238. /* Cache Controller */
  239. CCR_A: .long CCR
  240. MMUCR_A: .long MMUCR
  241. RWTCNT_A: .long WTCNT
  242. CCR_D: .long 0x0000090b
  243. CCR_D_2: .long 0x00000103
  244. MMUCR_D: .long 0x00000004
  245. MSTPCR0_D: .long 0x00001001
  246. MSTPCR2_D: .long 0xffffffff
  247. /* local Bus State Controller */
  248. MMSELR_A: .long MMSELR
  249. BCR_A: .long BCR
  250. CS0BCR_A: .long CS0BCR
  251. CS1BCR_A: .long CS1BCR
  252. CS2BCR_A: .long CS2BCR
  253. CS4BCR_A: .long CS4BCR
  254. CS5BCR_A: .long CS5BCR
  255. CS6BCR_A: .long CS6BCR
  256. CS0WCR_A: .long CS0WCR
  257. CS1WCR_A: .long CS1WCR
  258. CS2WCR_A: .long CS2WCR
  259. CS4WCR_A: .long CS4WCR
  260. CS5WCR_A: .long CS5WCR
  261. CS6WCR_A: .long CS6WCR
  262. CS5PCR_A: .long CS5PCR
  263. CS6PCR_A: .long CS6PCR
  264. MMSELR_D: .long 0xA5A50003
  265. BCR_D: .long 0x00000000
  266. CS0BCR_D: .long 0x77777770
  267. CS1BCR_D: .long 0x77777670
  268. CS2BCR_D: .long 0x77777770
  269. CS4BCR_D: .long 0x77777770
  270. CS5BCR_D: .long 0x77777670
  271. CS6BCR_D: .long 0x77777770
  272. CS0WCR_D: .long 0x00020006
  273. CS1WCR_D: .long 0x00232304
  274. CS2WCR_D: .long 0x7777770F
  275. CS4WCR_D: .long 0x7777770F
  276. CS5WCR_D: .long 0x00101006
  277. CS6WCR_D: .long 0x77777703
  278. CS5PCR_D: .long 0x77000000
  279. CS6PCR_D: .long 0x77000000
  280. REPEAT0_R3: .long 0x00002000
  281. REPEAT0_R1: .long 0x0000200