board.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
  9. * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
  10. * Copyright (C) 2019 DENX Software Engineering GmbH
  11. */
  12. #include <common.h>
  13. #include <spl.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/ddr_defs.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <power/tps65910.h>
  19. #include <jffs2/load_kernel.h>
  20. #include <mtd_node.h>
  21. #include <fdt_support.h>
  22. #include "board.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #ifdef CONFIG_SPL_BUILD
  25. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  26. /* DDR RAM defines */
  27. #define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
  28. #define OSC (V_OSCK / 1000000)
  29. const struct dpll_params dpll_ddr = {
  30. DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
  31. const struct dpll_params *get_dpll_ddr_params(void)
  32. {
  33. return &dpll_ddr;
  34. }
  35. const struct ctrl_ioregs ioregs = {
  36. .cm0ioctl = 0x18B,
  37. .cm1ioctl = 0x18B,
  38. .cm2ioctl = 0x18B,
  39. .dt0ioctl = 0x18B,
  40. .dt1ioctl = 0x18B,
  41. };
  42. static const struct cmd_control ddr3_cmd_ctrl_data = {
  43. .cmd0csratio = 0x80,
  44. .cmd0iclkout = 0x0,
  45. .cmd1csratio = 0x80,
  46. .cmd1iclkout = 0x0,
  47. .cmd2csratio = 0x80,
  48. .cmd2iclkout = 0x0,
  49. };
  50. enum {
  51. PHYCORE_R2_MT41K128M16JT_256MB,
  52. PHYCORE_R2_MT41K256M16TW107IT_512MB,
  53. PHYCORE_R2_MT41K512M16HA125IT_1024MB,
  54. };
  55. struct am335x_sdram_timings {
  56. struct emif_regs ddr3_emif_reg_data;
  57. struct ddr_data ddr3_data;
  58. };
  59. static struct am335x_sdram_timings physom_timings[] = {
  60. [PHYCORE_R2_MT41K128M16JT_256MB] = {
  61. .ddr3_emif_reg_data = {
  62. .sdram_config = 0x61C052B2,
  63. .ref_ctrl = 0x00000C30,
  64. .sdram_tim1 = 0x0AAAD4DB,
  65. .sdram_tim2 = 0x26437FDA,
  66. .sdram_tim3 = 0x501F83FF,
  67. .zq_config = 0x50074BE4,
  68. .emif_ddr_phy_ctlr_1 = 0x7,
  69. .ocp_config = 0x003d3d3d,
  70. },
  71. .ddr3_data = {
  72. .datardsratio0 = 0x36,
  73. .datawdsratio0 = 0x38,
  74. .datafwsratio0 = 0x99,
  75. .datawrsratio0 = 0x73,
  76. },
  77. },
  78. [PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
  79. .ddr3_emif_reg_data = {
  80. .sdram_config = 0x61C05332,
  81. .ref_ctrl = 0x00000C30,
  82. .sdram_tim1 = 0x0AAAD4DB,
  83. .sdram_tim2 = 0x266B7FDA,
  84. .sdram_tim3 = 0x501F867F,
  85. .zq_config = 0x50074BE4,
  86. .emif_ddr_phy_ctlr_1 = 0x7,
  87. .ocp_config = 0x003d3d3d,
  88. },
  89. .ddr3_data = {
  90. .datardsratio0 = 0x37,
  91. .datawdsratio0 = 0x38,
  92. .datafwsratio0 = 0x92,
  93. .datawrsratio0 = 0x72,
  94. },
  95. },
  96. [PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
  97. .ddr3_emif_reg_data = {
  98. .sdram_config = 0x61C053B2,
  99. .ref_ctrl = 0x00000C30,
  100. .sdram_tim1 = 0x0AAAD4DB,
  101. .sdram_tim2 = 0x268F7FDA,
  102. .sdram_tim3 = 0x501F88BF,
  103. .zq_config = 0x50074BE4,
  104. .emif_ddr_phy_ctlr_1 = 0x7,
  105. .ocp_config = 0x003d3d3d,
  106. },
  107. .ddr3_data = {
  108. .datardsratio0 = 0x38,
  109. .datawdsratio0 = 0x4d,
  110. .datafwsratio0 = 0x9d,
  111. .datawrsratio0 = 0x82,
  112. },
  113. },
  114. };
  115. void sdram_init(void)
  116. {
  117. /* Configure memory to maximum supported size for detection */
  118. int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
  119. config_ddr(DDR_CLK_MHZ, &ioregs,
  120. &physom_timings[ram_type_index].ddr3_data,
  121. &ddr3_cmd_ctrl_data,
  122. &physom_timings[ram_type_index].ddr3_emif_reg_data,
  123. 0);
  124. /* Detect memory physically present */
  125. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  126. CONFIG_MAX_RAM_BANK_SIZE);
  127. /* Reconfigure memory for actual detected size */
  128. switch (gd->ram_size) {
  129. case SZ_1G:
  130. ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
  131. break;
  132. case SZ_512M:
  133. ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
  134. break;
  135. case SZ_256M:
  136. default:
  137. ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
  138. break;
  139. }
  140. config_ddr(DDR_CLK_MHZ, &ioregs,
  141. &physom_timings[ram_type_index].ddr3_data,
  142. &ddr3_cmd_ctrl_data,
  143. &physom_timings[ram_type_index].ddr3_emif_reg_data,
  144. 0);
  145. }
  146. const struct dpll_params *get_dpll_mpu_params(void)
  147. {
  148. int ind = get_sys_clk_index();
  149. int freq = am335x_get_efuse_mpu_max_freq(cdev);
  150. switch (freq) {
  151. case MPUPLL_M_1000:
  152. return &dpll_mpu_opp[ind][5];
  153. case MPUPLL_M_800:
  154. return &dpll_mpu_opp[ind][4];
  155. case MPUPLL_M_720:
  156. return &dpll_mpu_opp[ind][3];
  157. case MPUPLL_M_600:
  158. return &dpll_mpu_opp[ind][2];
  159. case MPUPLL_M_500:
  160. return &dpll_mpu_opp100;
  161. case MPUPLL_M_300:
  162. return &dpll_mpu_opp[ind][0];
  163. }
  164. return &dpll_mpu_opp[ind][0];
  165. }
  166. static void scale_vcores_generic(int freq)
  167. {
  168. int sil_rev, mpu_vdd;
  169. /*
  170. * We use a TPS65910 PMIC. For all MPU frequencies we support we use a
  171. * CORE voltage of 1.10V. For MPU voltage we need to switch based on
  172. * the frequency we are running at.
  173. */
  174. if (power_tps65910_init(0))
  175. return;
  176. /*
  177. * Depending on MPU clock and PG we will need a different
  178. * VDD to drive at that speed.
  179. */
  180. sil_rev = readl(&cdev->deviceid) >> 28;
  181. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
  182. /* Tell the TPS65910 to use i2c */
  183. tps65910_set_i2c_control();
  184. /* First update MPU voltage. */
  185. if (tps65910_voltage_update(MPU, mpu_vdd))
  186. return;
  187. /* Second, update the CORE voltage. */
  188. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
  189. return;
  190. }
  191. void scale_vcores(void)
  192. {
  193. int freq;
  194. freq = am335x_get_efuse_mpu_max_freq(cdev);
  195. scale_vcores_generic(freq);
  196. }
  197. void set_uart_mux_conf(void)
  198. {
  199. enable_uart0_pin_mux();
  200. }
  201. void set_mux_conf_regs(void)
  202. {
  203. enable_i2c0_pin_mux();
  204. enable_board_pin_mux();
  205. }
  206. #endif
  207. /*
  208. * Basic board specific setup. Pinmux has been handled already.
  209. */
  210. int board_init(void)
  211. {
  212. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  213. return 0;
  214. }
  215. #ifdef CONFIG_OF_BOARD_SETUP
  216. int ft_board_setup(void *blob, bd_t *bd)
  217. {
  218. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  219. static const struct node_info nodes[] = {
  220. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  221. };
  222. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  223. #endif
  224. return 0;
  225. }
  226. #endif