spl.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Maintainer : Steve Sakoman <steve@sakoman.com>
  4. *
  5. * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
  6. * Richard Woodruff <r-woodruff2@ti.com>
  7. * Syed Mohammed Khasim <khasim@ti.com>
  8. * Sunil Kumar <sunilsaini05@gmail.com>
  9. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  10. *
  11. * (C) Copyright 2004-2008
  12. * Texas Instruments, <www.ti.com>
  13. */
  14. #include <asm/io.h>
  15. #include <asm/arch/mem.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include "overo.h"
  18. /*
  19. * Routine: get_board_mem_timings
  20. * Description: If we use SPL then there is no x-loader nor config header
  21. * so we have to setup the DDR timings ourself on both banks.
  22. */
  23. void get_board_mem_timings(struct board_sdrc_timings *timings)
  24. {
  25. timings->mr = MICRON_V_MR_165;
  26. switch (get_board_revision()) {
  27. case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
  28. timings->mcfg = MICRON_V_MCFG_165(256 << 20);
  29. timings->ctrla = MICRON_V_ACTIMA_165;
  30. timings->ctrlb = MICRON_V_ACTIMB_165;
  31. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  32. break;
  33. case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
  34. case REVISION_4:
  35. timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  36. timings->ctrla = MICRON_V_ACTIMA_200;
  37. timings->ctrlb = MICRON_V_ACTIMB_200;
  38. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  39. break;
  40. case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
  41. timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  42. timings->ctrla = HYNIX_V_ACTIMA_200;
  43. timings->ctrlb = HYNIX_V_ACTIMB_200;
  44. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  45. break;
  46. case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
  47. timings->mcfg = MCFG(512 << 20, 15);
  48. timings->ctrla = MICRON_V_ACTIMA_200;
  49. timings->ctrlb = MICRON_V_ACTIMB_200;
  50. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  51. break;
  52. default:
  53. timings->mcfg = MICRON_V_MCFG_165(128 << 20);
  54. timings->ctrla = MICRON_V_ACTIMA_165;
  55. timings->ctrlb = MICRON_V_ACTIMB_165;
  56. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  57. }
  58. }