kwbimage.cfg 5.1 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # (C) Copyright 2010
  4. # Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. # Refer doc/README.kwbimage for more details about how-to configure
  6. # and create kirkwood boot image
  7. #
  8. # Boot Media configurations
  9. BOOT_FROM spi # Boot from SPI flash
  10. DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
  11. # bit 3-0: MPPSel0 2, NF_IO[2]
  12. # bit 7-4: MPPSel1 2, NF_IO[3]
  13. # bit 12-8: MPPSel2 2, NF_IO[4]
  14. # bit 15-12: MPPSel3 2, NF_IO[5]
  15. # bit 19-16: MPPSel4 1, NF_IO[6]
  16. # bit 23-20: MPPSel5 1, NF_IO[7]
  17. # bit 27-24: MPPSel6 1, SYSRST_O
  18. # bit 31-28: MPPSel7 0, GPO[7]
  19. DATA 0xFFD10004 0x03303300
  20. DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
  21. # bit 3-0: MPPSel16 0, GPIO[16]
  22. # bit 7-4: MPPSel17 0, GPIO[17]
  23. # bit 12-8: MPPSel18 1, NF_IO[0]
  24. # bit 15-12: MPPSel19 1, NF_IO[1]
  25. # bit 19-16: MPPSel20 0, GPIO[20]
  26. # bit 23-20: MPPSel21 0, GPIO[21]
  27. # bit 27-24: MPPSel22 0, GPIO[22]
  28. # bit 31-28: MPPSel23 0, GPIO[23]
  29. DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
  30. DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
  31. DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
  32. # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
  33. # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
  34. #Dram initalization
  35. DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
  36. # bit13-0: 0x400 (DDR2 clks refresh rate)
  37. # bit23-14: zero
  38. # bit24: 1= enable exit self refresh mode on DDR access
  39. # bit25: 1 required
  40. # bit29-26: zero
  41. # bit31-30: 01
  42. DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
  43. # bit 3-0: 0 reserved
  44. # bit 4: 0=addr/cmd in smame cycle
  45. # bit 5: 0=clk is driven during self refresh, we don't care for APX
  46. # bit 6: 0=use recommended falling edge of clk for addr/cmd
  47. # bit14: 0=input buffer always powered up
  48. # bit18: 1=cpu lock transaction enabled
  49. # bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
  50. # bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
  51. # bit30-28: 3 required
  52. # bit31: 0=no additional STARTBURST delay
  53. DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
  54. # bit3-0: TRAS lsbs
  55. # bit7-4: TRCD
  56. # bit11- 8: TRP
  57. # bit15-12: TWR
  58. # bit19-16: TWTR
  59. # bit20: TRAS msb
  60. # bit23-21: 0x0
  61. # bit27-24: TRRD
  62. # bit31-28: TRTP
  63. DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
  64. # bit6-0: TRFC
  65. # bit8-7: TR2R
  66. # bit10-9: TR2W
  67. # bit12-11: TW2W
  68. # bit31-13: zero required
  69. DATA 0xFFD01410 0x0000000D # DDR Address Control
  70. # bit1-0: 01, Cs0width=x16
  71. # bit3-2: 11, Cs0size=1Gb
  72. # bit5-4: 00, Cs2width=nonexistent
  73. # bit7-6: 00, Cs1size =nonexistent
  74. # bit9-8: 00, Cs2width=nonexistent
  75. # bit11-10: 00, Cs2size =nonexistent
  76. # bit13-12: 00, Cs3width=nonexistent
  77. # bit15-14: 00, Cs3size =nonexistent
  78. # bit16: 0, Cs0AddrSel
  79. # bit17: 0, Cs1AddrSel
  80. # bit18: 0, Cs2AddrSel
  81. # bit19: 0, Cs3AddrSel
  82. # bit31-20: 0 required
  83. DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
  84. # bit0: 0, OpenPage enabled
  85. # bit31-1: 0 required
  86. DATA 0xFFD01418 0x00000000 # DDR Operation
  87. # bit3-0: 0x0, DDR cmd
  88. # bit31-4: 0 required
  89. DATA 0xFFD0141C 0x00000652 # DDR Mode
  90. DATA 0xFFD01420 0x00000044 # DDR Extended Mode
  91. # bit0: 0, DDR DLL enabled
  92. # bit1: 0, DDR drive strenght normal
  93. # bit2: 1, DDR ODT control lsd disabled
  94. # bit5-3: 000, required
  95. # bit6: 1, DDR ODT control msb, enabled
  96. # bit9-7: 000, required
  97. # bit10: 0, differential DQS enabled
  98. # bit11: 0, required
  99. # bit12: 0, DDR output buffer enabled
  100. # bit31-13: 0 required
  101. DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
  102. # bit2-0: 111, required
  103. # bit3 : 1 , MBUS Burst Chop disabled
  104. # bit6-4: 111, required
  105. # bit7 : 0
  106. # bit8 : 0 , no sample stage
  107. # bit9 : 0 , no half clock cycle addition to dataout
  108. # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
  109. # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
  110. # bit15-12: 1111 required
  111. # bit31-16: 0 required
  112. DATA 0xFFD01428 0x00074510
  113. DATA 0xFFD0147c 0x00007451
  114. DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
  115. DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
  116. # bit0: 1, Window enabled
  117. # bit1: 0, Write Protect disabled
  118. # bit3-2: 00, CS0 hit selected
  119. # bit23-4: ones, required
  120. # bit31-24: 0x07, Size (i.e. 128MB)
  121. DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
  122. DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
  123. DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
  124. DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
  125. # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
  126. # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
  127. DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
  128. # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
  129. # bit3-2: 00, ODT1 controlled by register
  130. # bit31-4: zero, required
  131. DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
  132. # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
  133. # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
  134. # bit9-8: 1, ODTEn, never active
  135. # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
  136. DATA 0xFFD01480 0x00000001 # DDR Initialization Control
  137. # bit0=1, enable DDR init upon this register write
  138. # End of Header extension
  139. DATA 0x0 0x0