fpga_config.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012
  4. * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <linux/errno.h>
  9. /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
  10. #define KM_XLX_PROGRAM_B_PIN 39
  11. #define BOCO_ADDR 0x10
  12. #define ID_REG 0x00
  13. #define BOCO2_ID 0x5b
  14. static int check_boco2(void)
  15. {
  16. int ret;
  17. u8 id;
  18. ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
  19. if (ret) {
  20. printf("%s: error reading the BOCO id !!\n", __func__);
  21. return ret;
  22. }
  23. return (id == BOCO2_ID);
  24. }
  25. static int boco_clear_bits(u8 reg, u8 flags)
  26. {
  27. int ret;
  28. u8 regval;
  29. /* give access to the EEPROM from FPGA */
  30. ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
  31. if (ret) {
  32. printf("%s: error reading the BOCO @%#x !!\n",
  33. __func__, reg);
  34. return ret;
  35. }
  36. regval &= ~flags;
  37. ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
  38. if (ret) {
  39. printf("%s: error writing the BOCO @%#x !!\n",
  40. __func__, reg);
  41. return ret;
  42. }
  43. return 0;
  44. }
  45. static int boco_set_bits(u8 reg, u8 flags)
  46. {
  47. int ret;
  48. u8 regval;
  49. /* give access to the EEPROM from FPGA */
  50. ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1);
  51. if (ret) {
  52. printf("%s: error reading the BOCO @%#x !!\n",
  53. __func__, reg);
  54. return ret;
  55. }
  56. regval |= flags;
  57. ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1);
  58. if (ret) {
  59. printf("%s: error writing the BOCO @%#x !!\n",
  60. __func__, reg);
  61. return ret;
  62. }
  63. return 0;
  64. }
  65. #define SPI_REG 0x06
  66. #define CFG_EEPROM 0x02
  67. #define FPGA_PROG 0x04
  68. #define FPGA_INIT_B 0x10
  69. #define FPGA_DONE 0x20
  70. static int fpga_done(void)
  71. {
  72. int ret = 0;
  73. u8 regval;
  74. /* this is only supported with the boco2 design */
  75. if (!check_boco2())
  76. return 0;
  77. ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &regval, 1);
  78. if (ret) {
  79. printf("%s: error reading the BOCO @%#x !!\n",
  80. __func__, SPI_REG);
  81. return 0;
  82. }
  83. return regval & FPGA_DONE ? 1 : 0;
  84. }
  85. int skip;
  86. int trigger_fpga_config(void)
  87. {
  88. int ret = 0;
  89. /* if the FPGA is already configured, we do not want to
  90. * reconfigure it */
  91. skip = 0;
  92. if (fpga_done()) {
  93. printf("PCIe FPGA config: skipped\n");
  94. skip = 1;
  95. return 0;
  96. }
  97. if (check_boco2()) {
  98. /* we have a BOCO2, this has to be triggered here */
  99. /* make sure the FPGA_can access the EEPROM */
  100. ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
  101. if (ret)
  102. return ret;
  103. /* trigger the config start */
  104. ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
  105. if (ret)
  106. return ret;
  107. /* small delay for the pulse */
  108. udelay(10);
  109. /* up signal for pulse end */
  110. ret = boco_set_bits(SPI_REG, FPGA_PROG);
  111. if (ret)
  112. return ret;
  113. /* finally, raise INIT_B to remove the config delay */
  114. ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
  115. if (ret)
  116. return ret;
  117. } else {
  118. /* we do it the old way, with the gpio pin */
  119. kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
  120. kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
  121. /* small delay for the pulse */
  122. udelay(10);
  123. kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
  124. }
  125. return 0;
  126. }
  127. int wait_for_fpga_config(void)
  128. {
  129. int ret = 0;
  130. u8 spictrl;
  131. u32 timeout = 20000;
  132. if (skip)
  133. return 0;
  134. if (!check_boco2()) {
  135. /* we do not have BOCO2, this is not really used */
  136. return 0;
  137. }
  138. printf("PCIe FPGA config:");
  139. do {
  140. ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
  141. if (ret) {
  142. printf("%s: error reading the BOCO spictrl !!\n",
  143. __func__);
  144. return ret;
  145. }
  146. if (timeout-- == 0) {
  147. printf(" FPGA_DONE timeout\n");
  148. return -EFAULT;
  149. }
  150. udelay(10);
  151. } while (!(spictrl & FPGA_DONE));
  152. printf(" done\n");
  153. return 0;
  154. }
  155. #if defined(KM_PCIE_RESET_MPP7)
  156. #define KM_PEX_RST_GPIO_PIN 7
  157. int fpga_reset(void)
  158. {
  159. if (!check_boco2()) {
  160. /* we do not have BOCO2, this is not really used */
  161. return 0;
  162. }
  163. printf("PCIe reset through GPIO7: ");
  164. /* apply PCIe reset via GPIO */
  165. kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
  166. kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
  167. kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
  168. udelay(1000*10);
  169. kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
  170. printf(" done\n");
  171. return 0;
  172. }
  173. #else
  174. #define PRST1 0x4
  175. #define PCIE_RST 0x10
  176. #define TRAFFIC_RST 0x04
  177. int fpga_reset(void)
  178. {
  179. int ret = 0;
  180. u8 resets;
  181. if (!check_boco2()) {
  182. /* we do not have BOCO2, this is not really used */
  183. return 0;
  184. }
  185. /* if we have skipped, we only want to reset the PCIe part */
  186. resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
  187. ret = boco_clear_bits(PRST1, resets);
  188. if (ret)
  189. return ret;
  190. /* small delay for the pulse */
  191. udelay(10);
  192. ret = boco_set_bits(PRST1, resets);
  193. if (ret)
  194. return ret;
  195. return 0;
  196. }
  197. #endif
  198. /* the FPGA was configured, we configure the BOCO2 so that the EEPROM
  199. * is available from the Bobcat SPI bus */
  200. int toggle_eeprom_spi_bus(void)
  201. {
  202. int ret = 0;
  203. if (!check_boco2()) {
  204. /* we do not have BOCO2, this is not really used */
  205. return 0;
  206. }
  207. ret = boco_set_bits(SPI_REG, CFG_EEPROM);
  208. if (ret)
  209. return ret;
  210. return 0;
  211. }