cherryhill.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <asm/arch/gpio.h>
  7. #include <asm/fsp1/fsp_support.h>
  8. static const struct gpio_family gpio_family[] = {
  9. GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
  10. VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
  11. /* end of the table */
  12. GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
  13. VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
  14. };
  15. static const struct gpio_pad gpio_pad[] = {
  16. GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
  17. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  18. NA, 29, NA, 0x4c38, NORTH),
  19. GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
  20. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  21. NA, 27, NA, 0x4c28, NORTH),
  22. GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
  23. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  24. NA, 20, NA, 0x4858, NORTH),
  25. GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
  26. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  27. NA, 37, NA, 0x5018, NORTH),
  28. GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
  29. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  30. NA, 42, NA, 0x5040, NORTH),
  31. GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
  32. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  33. NA, 35, NA, 0x5008, NORTH),
  34. GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
  35. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  36. NA, 40, NA, 0x5030, NORTH),
  37. GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
  38. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  39. NA, 45, NA, 0x5058, NORTH),
  40. GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
  41. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  42. NA, 34, NA, 0x5000, NORTH),
  43. GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
  44. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  45. NA, 38, NA, 0x5020, NORTH),
  46. GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
  47. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  48. NA, 43, NA, 0x5048, NORTH),
  49. GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
  50. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  51. NA, 36, NA, 0x5010, NORTH),
  52. GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
  53. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  54. NA, 41, NA, 0x5038, NORTH),
  55. GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW,
  56. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  57. NA, 39, NA, 0x5028, NORTH),
  58. GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW,
  59. NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  60. NA, 44, NA, 0x5050, NORTH),
  61. GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
  62. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  63. NA, 0, NA, 0x4400, NORTH),
  64. GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
  65. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  66. NA, 3, NA, 0x4418, NORTH),
  67. GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
  68. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  69. NA, 2, NA, 0x4438, NORTH),
  70. GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
  71. NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
  72. NA, 1, NA, 0x4408, NORTH),
  73. GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA,
  74. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  75. NA, 5, NA, 0x4428, NORTH),
  76. GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA,
  77. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  78. NA, 4, NA, 0x4420, NORTH),
  79. GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA,
  80. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  81. NA, 8, NA, 0x4440, NORTH),
  82. GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA,
  83. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  84. NA, 2, NA, 0x4410, NORTH),
  85. GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA,
  86. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  87. NA, 9 , NA, 0x4800, NORTH),
  88. GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA,
  89. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  90. NA, 13, NA, 0x4820, NORTH),
  91. GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA,
  92. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  93. NA, 18, NA, 0x4848, NORTH),
  94. GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA,
  95. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  96. NA, 11, NA, 0x4810, NORTH),
  97. GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA,
  98. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  99. NA, 16, NA, 0x4838, NORTH),
  100. GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA,
  101. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  102. NA, 14, NA, 0x4828, NORTH),
  103. GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA,
  104. TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,
  105. EN_EDGE_RX_DATA, NO_INVERSION,
  106. NA, 19, SCI, 0x4850, NORTH),
  107. GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA,
  108. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  109. NA, 12, SMI, 0x4818, NORTH),
  110. GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA,
  111. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  112. NA, 57, NA, 0x5458, NORTH),
  113. GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA,
  114. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  115. NA, 52, NA, 0x5430, NORTH),
  116. GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA,
  117. NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
  118. NA, 47, NA, 0x5408, NORTH),
  119. GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA,
  120. NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
  121. NA, 50, NA, 0x5420, NORTH),
  122. GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA,
  123. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  124. NA, 53, NA, 0x5438, NORTH),
  125. GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA,
  126. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  127. NA, 48, NA, 0x5410, NORTH),
  128. GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA,
  129. NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
  130. NA, 54, NA, 0x5440, NORTH),
  131. GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA,
  132. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  133. NA, 51, NA, 0x5428, NORTH),
  134. GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA,
  135. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  136. NA, 46, NA, 0x5400, NORTH),
  137. GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA,
  138. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  139. NA, 58, NA, 0x5460, NORTH),
  140. GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA,
  141. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  142. NA, 49, NA, 0x5418, NORTH),
  143. GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA,
  144. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  145. NA, 56, NA, 0x5450, NORTH),
  146. GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA,
  147. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  148. NA, 55, NA, 0x5448, NORTH),
  149. GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA,
  150. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  151. NA, 24, NA, 0x4c10, NORTH),
  152. GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA,
  153. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  154. NA, 10, NA, 0x4808, NORTH),
  155. GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA,
  156. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  157. NA, 15, NA, 0x4830, NORTH),
  158. GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA,
  159. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  160. NA, 17, NA, 0x4840, NORTH),
  161. GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA,
  162. TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,
  163. EN_RX_DATA, INV_RX_DATA,
  164. NA, 21, SCI, 0x4860, NORTH),
  165. GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA,
  166. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  167. NA, 23, NA, 0x4c08, NORTH),
  168. GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA,
  169. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  170. NA, 33, NA, 0x4c58, NORTH),
  171. GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA,
  172. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  173. NA, 31, NA, 0x4c48, NORTH),
  174. GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA,
  175. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  176. NA, 28, NA, 0x4c30, NORTH),
  177. GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA,
  178. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  179. NA, 26, NA, 0x4c20, NORTH),
  180. GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA,
  181. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  182. NA, 22, NA, 0x4c00, NORTH),
  183. GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA,
  184. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  185. NA, 18, NA, 0x4830, EAST),
  186. GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA,
  187. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  188. NA, 15, NA, 0x4818, EAST),
  189. GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA,
  190. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  191. NA, 21, NA, 0x4848, EAST),
  192. GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA,
  193. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  194. NA, 12, NA, 0x4800, EAST),
  195. GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA,
  196. NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,
  197. NA, 19, NA, 0x4838, EAST),
  198. GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA,
  199. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  200. NA, 16, NA, 0x4820, EAST),
  201. GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA,
  202. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  203. NA, 22, NA, 0x4850, EAST),
  204. GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA,
  205. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  206. NA, 13, NA, 0x4808, EAST),
  207. GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA,
  208. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  209. NA, 20, NA, 0x4840, EAST),
  210. GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA,
  211. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  212. NA, 17, NA, 0x4828, EAST),
  213. GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA,
  214. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  215. NA, 23, NA, 0x4858, EAST),
  216. GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA,
  217. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  218. NA, 14, NA, 0x4810, EAST),
  219. GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA,
  220. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  221. NA, 4, NA, 0x4420, EAST),
  222. GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA,
  223. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  224. NA, 1, NA, 0x4408, EAST),
  225. GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA,
  226. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  227. NA, 5, NA, 0x4428, EAST),
  228. GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA,
  229. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  230. NA, 7, NA, 0x4438, EAST),
  231. GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA,
  232. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  233. NA, 3, NA, 0x4418, EAST),
  234. GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA,
  235. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  236. NA, 0, NA, 0x4400, EAST),
  237. GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA,
  238. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  239. NA, 9, NA, 0x4448, EAST),
  240. GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA,
  241. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  242. NA, 6, NA, 0x4430, EAST),
  243. GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA,
  244. NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
  245. NA, 10, NA, 0x4450, EAST),
  246. GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA,
  247. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  248. NA, 11, NA, 0x4458, EAST),
  249. GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA,
  250. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  251. NA, 2, NA, 0x4410, EAST),
  252. GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH,
  253. NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
  254. NA, 9, NA, 0x4808, SOUTHEAST),
  255. GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH,
  256. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  257. NA, 16, NA, 0x4840, SOUTHEAST),
  258. GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH,
  259. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  260. NA, 10, NA, 0x4810, SOUTHEAST),
  261. GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH,
  262. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  263. NA, 17, NA, 0x4848, SOUTHEAST),
  264. GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH,
  265. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  266. NA, 13, NA, 0x4828, SOUTHEAST),
  267. GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH,
  268. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  269. NA, 19, NA, 0x4858, SOUTHEAST),
  270. GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH,
  271. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  272. NA, 41, NA, 0x5438, SOUTHEAST),
  273. GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH,
  274. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  275. NA, 39, NA, 0x5428, SOUTHEAST),
  276. GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH,
  277. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  278. NA, 37, NA, 0x5418, SOUTHEAST),
  279. GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH,
  280. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  281. NA, 42, NA, 0x5440, SOUTHEAST),
  282. GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA,
  283. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  284. NA, 43, NA, 0x5448, SOUTHEAST),
  285. GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA,
  286. TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,
  287. EN_RX_DATA, INV_RX_DATA,
  288. NA, 46, NA, 0x5810, SOUTHEAST),
  289. GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA,
  290. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  291. NA, 48, NA, 0x5820, SOUTHEAST),
  292. GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA,
  293. NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
  294. NA, 32, NA, 0x5030, SOUTHEAST),
  295. GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA,
  296. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  297. NA, 30, NA, 0x5020, SOUTHEAST),
  298. GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA,
  299. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  300. NA, 28, NA, 0x5010, SOUTHEAST),
  301. GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA,
  302. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  303. NA, 33, NA, 0x5038, SOUTHEAST),
  304. GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA,
  305. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  306. NA, 26, NA, 0x5000, SOUTHEAST),
  307. GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA,
  308. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  309. NA, 31, NA, 0x5028, SOUTHEAST),
  310. GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA,
  311. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  312. NA, 27, NA, 0x5008, SOUTHEAST),
  313. GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA,
  314. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  315. NA, 29, NA, 0x5018, SOUTHEAST),
  316. GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA,
  317. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  318. NA, 0, NA, 0x4400, SOUTHEAST),
  319. GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA,
  320. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  321. NA, 1, NA, 0x4410, SOUTHEAST),
  322. GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA,
  323. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  324. NA, 7, NA, 0x4438, SOUTHEAST),
  325. GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA,
  326. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  327. NA, 4, NA, 0x4420, SOUTHEAST),
  328. GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA,
  329. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  330. NA, 3, NA, 0x4418, SOUTHEAST),
  331. GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA,
  332. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  333. NA, 6, NA, 0x4430, SOUTHEAST),
  334. GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA,
  335. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  336. NA, 52, NA, 0x5840, SOUTHEAST),
  337. GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA,
  338. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  339. NA, 5, NA, 0x4428, SOUTHEAST),
  340. GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA,
  341. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  342. NA, 1, NA, 0x4408, SOUTHEAST),
  343. GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA,
  344. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  345. NA, 54, NA, 0x5850, SOUTHEAST),
  346. GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA,
  347. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  348. NA, 50, NA, 0x5830, SOUTHEAST),
  349. GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA,
  350. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  351. NA, 21, NA, 0x4c08, SOUTHEAST),
  352. GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA,
  353. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  354. NA, 24, NA, 0x4c20, SOUTHEAST),
  355. GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA,
  356. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  357. NA, 25, NA, 0x4c28, SOUTHEAST),
  358. GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA,
  359. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  360. NA, 20, NA, 0x4c00, SOUTHEAST),
  361. GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA,
  362. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  363. NA, 23, NA, 0x4c18, SOUTHEAST),
  364. GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA,
  365. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  366. NA, 22, NA, 0x4c10, SOUTHEAST),
  367. GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA,
  368. NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
  369. NA, 47, NA, 0x5818, SOUTHEAST),
  370. GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA,
  371. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  372. NA, 12, NA, 0x4820, SOUTHEAST),
  373. GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA,
  374. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  375. NA, 15, NA, 0x4838, SOUTHEAST),
  376. GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA,
  377. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  378. NA, 18, NA, 0x4850, SOUTHEAST),
  379. GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA,
  380. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  381. NA, 11, NA, 0x4818, SOUTHEAST),
  382. GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA,
  383. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  384. NA, 14, NA, 0x4830, SOUTHEAST),
  385. GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA,
  386. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  387. NA, 8, NA, 0x4800, SOUTHEAST),
  388. GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA,
  389. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  390. NA, 36, NA, 0x5410, SOUTHEAST),
  391. GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA,
  392. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  393. NA, 35, NA, 0x5408, SOUTHEAST),
  394. GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA,
  395. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  396. NA, 40, NA, 0x5430, SOUTHEAST),
  397. GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA,
  398. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  399. NA, 34, NA, 0x5400, SOUTHEAST),
  400. GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA,
  401. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  402. NA, 38, NA, 0x5420, SOUTHEAST),
  403. GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA,
  404. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  405. NA, 49, NA, 0x5828, SOUTHEAST),
  406. GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA,
  407. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  408. NA, 44, NA, 0x5800, SOUTHEAST),
  409. GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA,
  410. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  411. NA, 2, NA, 0x4410, SOUTHWEST),
  412. GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA,
  413. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  414. NA, 6, NA, 0x4430, SOUTHWEST),
  415. GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA,
  416. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  417. NA, 4, NA, 0x4420, SOUTHWEST),
  418. GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA,
  419. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  420. NA, 7, NA, 0x4438, SOUTHWEST),
  421. GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA,
  422. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  423. NA, 1, NA, 0x4408, SOUTHWEST),
  424. GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA,
  425. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  426. NA, 5, NA, 0x4428, SOUTHWEST),
  427. GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA,
  428. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  429. NA, 0, NA, 0x4400, SOUTHWEST),
  430. GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA,
  431. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  432. NA, 3, NA, 0x4418, SOUTHWEST),
  433. GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA,
  434. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  435. NA, 16, NA, 0x4c00, SOUTHWEST),
  436. GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA,
  437. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  438. NA, 23, NA, 0x4c38, SOUTHWEST),
  439. GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA,
  440. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  441. NA, 20, NA, 0x4c20, SOUTHWEST),
  442. GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA,
  443. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  444. NA, 17, NA, 0x4c08, SOUTHWEST),
  445. GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA,
  446. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  447. NA, 18, NA, 0x4c10, SOUTHWEST),
  448. GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA,
  449. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  450. NA, 22, NA, 0x4c30, SOUTHWEST),
  451. GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA,
  452. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  453. NA, 19, NA, 0x4c18, SOUTHWEST),
  454. GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA,
  455. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  456. NA, 21, NA, 0x4c28, SOUTHWEST),
  457. GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA,
  458. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  459. NA, 11, NA, 0x4818, SOUTHWEST),
  460. GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA,
  461. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  462. NA, 8, NA, 0x4800, SOUTHWEST),
  463. GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA,
  464. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  465. NA, 9, NA, 0x4808, SOUTHWEST),
  466. GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA,
  467. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  468. NA, 13, NA, 0x4828, SOUTHWEST),
  469. GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA,
  470. NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
  471. NA, 15, NA, 0x4838, SOUTHWEST),
  472. GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA,
  473. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  474. NA, 12, NA, 0x4820, SOUTHWEST),
  475. GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA,
  476. NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
  477. NA, 10, NA, 0x4810, SOUTHWEST),
  478. GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA,
  479. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  480. NA, 14, NA, 0x4830, SOUTHWEST),
  481. GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA,
  482. NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
  483. NA, 29, NA, 0x5028, SOUTHWEST),
  484. GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA,
  485. NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
  486. NA, 25, NA, 0x5008, SOUTHWEST),
  487. GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA,
  488. NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
  489. NA, 28, NA, 0x5020, SOUTHWEST),
  490. GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA,
  491. NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
  492. NA, 31, NA, 0x5038, SOUTHWEST),
  493. GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA,
  494. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  495. NA, 50, NA, 0x5c10, SOUTHWEST),
  496. GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA,
  497. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  498. NA, 54, NA, 0x5c30, SOUTHWEST),
  499. GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA,
  500. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  501. NA, 52, NA, 0x5c20, SOUTHWEST),
  502. GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA,
  503. NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
  504. NA, 55, NA, 0x5C38, SOUTHWEST),
  505. GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
  506. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  507. NA, 48, NA, 0x5c00, SOUTHWEST),
  508. GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
  509. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  510. NA, 49, NA, 0x5c08, SOUTHWEST),
  511. GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
  512. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  513. NA, 51, NA, 0x5c18, SOUTHWEST),
  514. GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
  515. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  516. NA, 53, NA, 0x5c28, SOUTHWEST),
  517. GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA,
  518. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  519. NA, 40, NA, 0x5800, SOUTHWEST),
  520. GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA,
  521. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  522. NA, 41, NA, 0x5808, SOUTHWEST),
  523. GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
  524. NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
  525. NA, 43, NA, 0x5818, SOUTHWEST),
  526. GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
  527. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  528. NA, 45, NA, 0x5828, SOUTHWEST),
  529. GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
  530. NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
  531. NA, 42, NA, 0x5810, SOUTHWEST),
  532. GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
  533. NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  534. NA, 44, NA, 0x5820, SOUTHWEST),
  535. GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
  536. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  537. NA, 46, NA, 0x5830, SOUTHWEST),
  538. GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
  539. NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
  540. NA, 47, NA, 0x5838, SOUTHWEST),
  541. GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
  542. NA, NA, NA, NA, NA, NA, NA, NA,
  543. NA, 48, NA, 0x5c00, SOUTHWEST),
  544. GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
  545. NA, NA, NA, NA, NA, NA, NA, NA,
  546. NA, 49, NA, 0x5c08, SOUTHWEST),
  547. GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
  548. NA, NA, NA, NA, NA, NA, NA, NA,
  549. NA, 51, NA, 0x5c18, SOUTHWEST),
  550. GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
  551. NA, NA, NA, NA, NA, NA, NA, NA,
  552. NA, 53, NA, 0x5c28, SOUTHWEST),
  553. GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA,
  554. NA, NA, NA, NA, NA, NA, NA,
  555. NA, 40, NA, 0x5800, SOUTHWEST),
  556. GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA,
  557. NA, NA, NA, NA, NA, NA, NA,
  558. NA, 41, NA, 0x5808, SOUTHWEST),
  559. GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
  560. NA, NA, NA, ENABLE, NA, NA, NA, NA,
  561. NA, 43, NA, 0x5818, SOUTHWEST),
  562. GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
  563. NA, NA, NA, NA, NA, NA, NA, NA,
  564. NA, 45, NA, 0x5828, SOUTHWEST),
  565. GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
  566. NA, NA, NA, ENABLE, NA, NA, NA, NA,
  567. NA, 42, NA, 0x5810, SOUTHWEST),
  568. GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
  569. NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,
  570. NA, 44, NA, 0x5820, SOUTHWEST),
  571. GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
  572. NA, NA, P_20K_H, NA, NA, NA, NA, NA,
  573. NA, 46, NA, 0x5830, SOUTHWEST),
  574. GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
  575. NA, NA, P_20K_H, NA, NA, NA, NA, NA,
  576. NA, 47, NA, 0x5838, SOUTHWEST),
  577. /* end of the table */
  578. GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA,
  579. NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
  580. NA, 0, NA, 0, TERMINATOR),
  581. };
  582. void update_fsp_gpio_configs(const struct gpio_family **family,
  583. const struct gpio_pad **pad)
  584. {
  585. *family = gpio_family;
  586. *pad = gpio_pad;
  587. }