hikey960.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Linaro
  4. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/hi3660.h>
  11. #include <asm/armv8/mmu.h>
  12. #include <asm/psci.h>
  13. #include <linux/arm-smccc.h>
  14. #include <linux/psci.h>
  15. #define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
  16. #define PMIC_VSEL_MASK 0x7
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  19. #include <dm/platform_data/serial_pl01x.h>
  20. static const struct pl01x_serial_platdata serial_platdata = {
  21. .base = HI3660_UART6_BASE,
  22. .type = TYPE_PL011,
  23. .clock = 19200000
  24. };
  25. U_BOOT_DEVICE(hikey960_serial0) = {
  26. .name = "serial_pl01x",
  27. .platdata = &serial_platdata,
  28. };
  29. #endif
  30. static struct mm_region hikey_mem_map[] = {
  31. {
  32. .virt = 0x0UL, /* DDR */
  33. .phys = 0x0UL,
  34. .size = 0xC0000000UL,
  35. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  36. PTE_BLOCK_INNER_SHARE
  37. }, {
  38. .virt = 0xE0000000UL, /* Peripheral block */
  39. .phys = 0xE0000000UL,
  40. .size = 0x20000000UL,
  41. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  42. PTE_BLOCK_NON_SHARE |
  43. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  44. }, {
  45. /* List terminator */
  46. 0,
  47. }
  48. };
  49. struct mm_region *mem_map = hikey_mem_map;
  50. int board_early_init_f(void)
  51. {
  52. return 0;
  53. }
  54. int misc_init_r(void)
  55. {
  56. return 0;
  57. }
  58. int dram_init(void)
  59. {
  60. gd->ram_size = PHYS_SDRAM_1_SIZE;
  61. return 0;
  62. }
  63. int dram_init_banksize(void)
  64. {
  65. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  66. gd->bd->bi_dram[0].size = gd->ram_size;
  67. return 0;
  68. }
  69. void hikey960_sd_init(void)
  70. {
  71. u32 data;
  72. /* Enable FPLL0 */
  73. data = readl(SCTRL_SCFPLLCTRL0);
  74. data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
  75. writel(data, SCTRL_SCFPLLCTRL0);
  76. /* Configure LDO16 */
  77. data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
  78. PMIC_VSEL_MASK;
  79. data |= 6;
  80. writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
  81. data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
  82. data |= 2;
  83. writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
  84. udelay(100);
  85. /* Configure LDO9 */
  86. data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
  87. PMIC_VSEL_MASK;
  88. data |= 5;
  89. writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
  90. data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
  91. data |= 2;
  92. writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
  93. udelay(100);
  94. /* GPIO CD */
  95. writel(0, PINMUX4_SDDET);
  96. /* SD Pinconf */
  97. writel(15 << 4, PINCONF3_SDCLK);
  98. writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
  99. writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
  100. writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
  101. writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
  102. writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
  103. /* Set SD clock mux */
  104. do {
  105. data = readl(CRG_REG_BASE + 0xb8);
  106. data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
  107. writel(data, CRG_REG_BASE + 0xb8);
  108. data = readl(CRG_REG_BASE + 0xb8);
  109. } while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
  110. /* Take SD out of reset */
  111. writel(1 << 18, CRG_PERRSTDIS4);
  112. do {
  113. data = readl(CRG_PERRSTSTAT4);
  114. } while ((data & (1 << 18)) == (1 << 18));
  115. /* Enable hclk_gate_sd */
  116. data = readl(CRG_REG_BASE + 0);
  117. data |= (1 << 30);
  118. writel(data, CRG_REG_BASE + 0);
  119. /* Enable clk_andgt_mmc */
  120. data = readl(CRG_REG_BASE + 0xf4);
  121. data |= ((1 << 3) | (1 << 3 << 16));
  122. writel(data, CRG_REG_BASE + 0xf4);
  123. /* Enable clk_gate_sd */
  124. data = readl(CRG_PEREN4);
  125. data |= (1 << 17);
  126. writel(data, CRG_PEREN4);
  127. do {
  128. data = readl(CRG_PERCLKEN4);
  129. } while ((data & (1 << 17)) != (1 << 17));
  130. }
  131. static void show_psci_version(void)
  132. {
  133. struct arm_smccc_res res;
  134. arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
  135. printf("PSCI: v%ld.%ld\n",
  136. PSCI_VERSION_MAJOR(res.a0),
  137. PSCI_VERSION_MINOR(res.a0));
  138. }
  139. int board_init(void)
  140. {
  141. /* Init SD */
  142. hikey960_sd_init();
  143. show_psci_version();
  144. return 0;
  145. }
  146. void reset_cpu(ulong addr)
  147. {
  148. psci_system_reset();
  149. }