ahci.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Calxeda, Inc.
  4. */
  5. #include <common.h>
  6. #include <ahci.h>
  7. #include <asm/io.h>
  8. #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
  9. #define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
  10. #define CPHY_BASE 0xfff58000
  11. #define CPHY_WIDTH 0x1000
  12. #define CPHY_DTE_XS 5
  13. #define CPHY_MII 31
  14. #define SERDES_CR_CTL 0x80a0
  15. #define SERDES_CR_ADDR 0x80a1
  16. #define SERDES_CR_DATA 0x80a2
  17. #define CR_BUSY 0x0001
  18. #define CR_START 0x0001
  19. #define CR_WR_RDN 0x0002
  20. #define CPHY_TX_INPUT_STS 0x2001
  21. #define CPHY_RX_INPUT_STS 0x2002
  22. #define CPHY_SATA_TX_OVERRIDE_BIT 0x8000
  23. #define CPHY_SATA_RX_OVERRIDE_BIT 0x4000
  24. #define CPHY_TX_INPUT_OVERRIDE 0x2004
  25. #define CPHY_RX_INPUT_OVERRIDE 0x2005
  26. #define SPHY_LANE 0x100
  27. #define SPHY_HALF_RATE 0x0001
  28. #define CPHY_SATA_DPLL_MODE 0x0700
  29. #define CPHY_SATA_DPLL_SHIFT 8
  30. #define CPHY_SATA_TX_ATTEN 0x1c00
  31. #define CPHY_SATA_TX_ATTEN_SHIFT 10
  32. #define HB_SREG_SATA_ATTEN 0xfff3cf24
  33. #define SATA_PORT_BASE 0xffe08000
  34. #define SATA_VERSIONR 0xf8
  35. #define SATA_HB_VERSION 0x3332302a
  36. static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
  37. {
  38. u32 data;
  39. writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
  40. data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
  41. return data;
  42. }
  43. static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
  44. {
  45. writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
  46. writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
  47. }
  48. static u32 combo_phy_read(u8 phy, u32 addr)
  49. {
  50. u8 dev = CPHY_DTE_XS;
  51. if (phy == 5)
  52. dev = CPHY_MII;
  53. while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
  54. udelay(5);
  55. __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
  56. __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
  57. while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
  58. udelay(5);
  59. return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
  60. }
  61. static void combo_phy_write(u8 phy, u32 addr, u32 data)
  62. {
  63. u8 dev = CPHY_DTE_XS;
  64. if (phy == 5)
  65. dev = CPHY_MII;
  66. while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
  67. udelay(5);
  68. __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
  69. __combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
  70. __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
  71. }
  72. static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
  73. {
  74. u32 tmp;
  75. tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
  76. tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
  77. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  78. tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
  79. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  80. tmp &= ~CPHY_SATA_DPLL_MODE;
  81. tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
  82. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  83. }
  84. static void cphy_tx_attenuation_override(u8 phy, u8 lane)
  85. {
  86. u32 val;
  87. u32 tmp;
  88. u8 shift;
  89. shift = ((phy == 5) ? 4 : lane) * 4;
  90. val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
  91. if (val & 0x8)
  92. return;
  93. tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
  94. tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
  95. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  96. tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
  97. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  98. tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
  99. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  100. }
  101. static void cphy_disable_port_overrides(u8 port)
  102. {
  103. u32 tmp;
  104. u8 lane = 0, phy = 0;
  105. if (port == 0)
  106. phy = 5;
  107. else if (port < 5)
  108. lane = port - 1;
  109. else
  110. return;
  111. tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
  112. tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
  113. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  114. tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
  115. tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
  116. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  117. }
  118. void cphy_disable_overrides(void)
  119. {
  120. int i;
  121. u32 port_map;
  122. port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
  123. for (i = 0; i < 5; i++) {
  124. if (port_map & (1 << i))
  125. cphy_disable_port_overrides(i);
  126. }
  127. }
  128. static void cphy_override_lane(u8 port)
  129. {
  130. u32 tmp, k = 0;
  131. u8 lane = 0, phy = 0;
  132. if (port == 0)
  133. phy = 5;
  134. else if (port < 5)
  135. lane = port - 1;
  136. else
  137. return;
  138. do {
  139. tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
  140. lane * SPHY_LANE);
  141. } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
  142. cphy_spread_spectrum_override(phy, lane, 3);
  143. cphy_tx_attenuation_override(phy, lane);
  144. }
  145. #define WAIT_MS_LINKUP 4
  146. int ahci_link_up(struct ahci_uc_priv *probe_ent, int port)
  147. {
  148. u32 tmp;
  149. int j = 0;
  150. u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
  151. u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
  152. SATA_HB_VERSION ? 1 : 0;
  153. /* Bring up SATA link.
  154. * SATA link bringup time is usually less than 1 ms; only very
  155. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  156. */
  157. while (j < WAIT_MS_LINKUP) {
  158. if (is_highbank && (j == 0)) {
  159. cphy_disable_port_overrides(port);
  160. writel(0x301, port_mmio + PORT_SCR_CTL);
  161. udelay(1000);
  162. writel(0x300, port_mmio + PORT_SCR_CTL);
  163. udelay(1000);
  164. cphy_override_lane(port);
  165. }
  166. tmp = readl(port_mmio + PORT_SCR_STAT);
  167. if ((tmp & 0xf) == 0x3)
  168. return 0;
  169. udelay(1000);
  170. j++;
  171. if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
  172. j = 0; /* retry phy reset */
  173. }
  174. return 1;
  175. }