duovero.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Gumstix Inc. <www.gumstix.com>
  5. * Maintainer: Ash Charles <ash@gumstix.com>
  6. */
  7. #include <common.h>
  8. #include <netdev.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/mmc_host_def.h>
  11. #include <twl6030.h>
  12. #include <asm/emif.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/gpio.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-types.h>
  17. #include "duovero_mux_data.h"
  18. #define WIFI_EN 43
  19. #if defined(CONFIG_CMD_NET)
  20. #define SMSC_NRESET 45
  21. static void setup_net_chip(void);
  22. #endif
  23. #ifdef CONFIG_USB_EHCI_HCD
  24. #include <usb.h>
  25. #include <asm/arch/ehci.h>
  26. #include <asm/ehci-omap.h>
  27. #endif
  28. DECLARE_GLOBAL_DATA_PTR;
  29. const struct omap_sysinfo sysinfo = {
  30. "Board: duovero\n"
  31. };
  32. struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
  33. /**
  34. * @brief board_init
  35. *
  36. * @return 0
  37. */
  38. int board_init(void)
  39. {
  40. gpmc_init();
  41. gd->bd->bi_arch_number = MACH_TYPE_DUOVERO;
  42. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  43. return 0;
  44. }
  45. /**
  46. * @brief misc_init_r - Configure board specific configurations
  47. * such as power configurations, ethernet initialization as phase2 of
  48. * boot sequence
  49. *
  50. * @return 0
  51. */
  52. int misc_init_r(void)
  53. {
  54. int ret = 0;
  55. u8 val;
  56. /* wifi setup: first enable 32Khz clock from 6030 pmic */
  57. val = 0xe1;
  58. ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
  59. if (ret)
  60. printf("Failed to enable 32Khz clock to wifi module\n");
  61. /* then setup WIFI_EN as an output pin and send reset pulse */
  62. if (!gpio_request(WIFI_EN, "")) {
  63. gpio_direction_output(WIFI_EN, 0);
  64. gpio_set_value(WIFI_EN, 1);
  65. udelay(1);
  66. gpio_set_value(WIFI_EN, 0);
  67. udelay(1);
  68. gpio_set_value(WIFI_EN, 1);
  69. }
  70. #if defined(CONFIG_CMD_NET)
  71. setup_net_chip();
  72. #endif
  73. return 0;
  74. }
  75. void set_muxconf_regs(void)
  76. {
  77. do_set_mux((*ctrl)->control_padconf_core_base,
  78. core_padconf_array_essential,
  79. sizeof(core_padconf_array_essential) /
  80. sizeof(struct pad_conf_entry));
  81. do_set_mux((*ctrl)->control_padconf_wkup_base,
  82. wkup_padconf_array_essential,
  83. sizeof(wkup_padconf_array_essential) /
  84. sizeof(struct pad_conf_entry));
  85. do_set_mux((*ctrl)->control_padconf_core_base,
  86. core_padconf_array_non_essential,
  87. sizeof(core_padconf_array_non_essential) /
  88. sizeof(struct pad_conf_entry));
  89. do_set_mux((*ctrl)->control_padconf_wkup_base,
  90. wkup_padconf_array_non_essential,
  91. sizeof(wkup_padconf_array_non_essential) /
  92. sizeof(struct pad_conf_entry));
  93. }
  94. #if defined(CONFIG_MMC)
  95. int board_mmc_init(bd_t *bis)
  96. {
  97. return omap_mmc_init(0, 0, 0, -1, -1);
  98. }
  99. #if !defined(CONFIG_SPL_BUILD)
  100. void board_mmc_power_init(void)
  101. {
  102. twl6030_power_mmc_init(0);
  103. }
  104. #endif
  105. #endif
  106. #if defined(CONFIG_CMD_NET)
  107. #define GPMC_SIZE_16M 0xF
  108. #define GPMC_BASEADDR_MASK 0x3F
  109. #define GPMC_CS_ENABLE 0x1
  110. static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
  111. u32 base, u32 size)
  112. {
  113. writel(0, &cs->config7);
  114. sdelay(1000);
  115. /* Delay for settling */
  116. writel(gpmc_config[0], &cs->config1);
  117. writel(gpmc_config[1], &cs->config2);
  118. writel(gpmc_config[2], &cs->config3);
  119. writel(gpmc_config[3], &cs->config4);
  120. writel(gpmc_config[4], &cs->config5);
  121. writel(gpmc_config[5], &cs->config6);
  122. /*
  123. * Enable the config. size is the CS size and goes in
  124. * bits 11:8. We set bit 6 to enable this CS and the base
  125. * address goes into bits 5:0.
  126. */
  127. writel((size << 8) | (GPMC_CS_ENABLE << 6) |
  128. ((base >> 24) & GPMC_BASEADDR_MASK),
  129. &cs->config7);
  130. sdelay(2000);
  131. }
  132. /* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
  133. #define NET_LAN9221_GPMC_CONFIG1 0x2a001203
  134. #define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
  135. #define NET_LAN9221_GPMC_CONFIG3 0x00020200
  136. #define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
  137. #define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
  138. #define NET_LAN9221_GPMC_CONFIG6 0x8a070707
  139. #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
  140. /* GPMC definitions for LAN9221 chips on expansion boards */
  141. static const u32 gpmc_lan_config[] = {
  142. NET_LAN9221_GPMC_CONFIG1,
  143. NET_LAN9221_GPMC_CONFIG2,
  144. NET_LAN9221_GPMC_CONFIG3,
  145. NET_LAN9221_GPMC_CONFIG4,
  146. NET_LAN9221_GPMC_CONFIG5,
  147. NET_LAN9221_GPMC_CONFIG6,
  148. /*CONFIG7- computed as params */
  149. };
  150. /*
  151. * Routine: setup_net_chip
  152. * Description: Setting up the configuration GPMC registers specific to the
  153. * Ethernet hardware.
  154. */
  155. static void setup_net_chip(void)
  156. {
  157. enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
  158. GPMC_SIZE_16M);
  159. /* Make GPIO SMSC_NRESET as output pin and send reset pulse */
  160. if (!gpio_request(SMSC_NRESET, "")) {
  161. gpio_direction_output(SMSC_NRESET, 0);
  162. gpio_set_value(SMSC_NRESET, 1);
  163. udelay(1);
  164. gpio_set_value(SMSC_NRESET, 0);
  165. udelay(1);
  166. gpio_set_value(SMSC_NRESET, 1);
  167. }
  168. }
  169. #endif
  170. int board_eth_init(bd_t *bis)
  171. {
  172. int rc = 0;
  173. #ifdef CONFIG_SMC911X
  174. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  175. #endif
  176. return rc;
  177. }
  178. #ifdef CONFIG_USB_EHCI_HCD
  179. static struct omap_usbhs_board_data usbhs_bdata = {
  180. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  181. .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
  182. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  183. };
  184. int ehci_hcd_init(int index, enum usb_init_type init,
  185. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  186. {
  187. int ret;
  188. unsigned int utmi_clk;
  189. u32 auxclk, altclksrc;
  190. /* Now we can enable our port clocks */
  191. utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
  192. utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
  193. setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
  194. auxclk = readl(&scrm->auxclk3);
  195. /* Select sys_clk */
  196. auxclk &= ~AUXCLK_SRCSELECT_MASK;
  197. auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
  198. /* Set the divisor to 2 */
  199. auxclk &= ~AUXCLK_CLKDIV_MASK;
  200. auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
  201. /* Request auxilary clock #3 */
  202. auxclk |= AUXCLK_ENABLE_MASK;
  203. writel(auxclk, &scrm->auxclk3);
  204. altclksrc = readl(&scrm->altclksrc);
  205. /* Activate alternate system clock supplier */
  206. altclksrc &= ~ALTCLKSRC_MODE_MASK;
  207. altclksrc |= ALTCLKSRC_MODE_ACTIVE;
  208. /* enable clocks */
  209. altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
  210. writel(altclksrc, &scrm->altclksrc);
  211. ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
  212. if (ret < 0)
  213. return ret;
  214. return 0;
  215. }
  216. int ehci_hcd_stop(int index)
  217. {
  218. return omap_ehci_hcd_stop();
  219. }
  220. #endif
  221. /*
  222. * get_board_rev() - get board revision
  223. */
  224. u32 get_board_rev(void)
  225. {
  226. return 0x20;
  227. }