strider.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <hwconfig.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <spi.h>
  12. #include <linux/libfdt.h>
  13. #include <fdt_support.h>
  14. #include <pci.h>
  15. #include <mpc83xx.h>
  16. #include <fsl_esdhc.h>
  17. #include <asm/io.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_mpc83xx_serdes.h>
  20. #include "mpc8308.h"
  21. #include <gdsys_fpga.h>
  22. #include "../common/adv7611.h"
  23. #include "../common/ch7301.h"
  24. #include "../common/dp501.h"
  25. #include "../common/ioep-fpga.h"
  26. #include "../common/mclink.h"
  27. #include "../common/osd.h"
  28. #include "../common/phy.h"
  29. #include "../common/fanctrl.h"
  30. #include <pca953x.h>
  31. #include <pca9698.h>
  32. #include <miiphy.h>
  33. #define MAX_MUX_CHANNELS 2
  34. enum {
  35. MCFPGA_DONE = 1 << 0,
  36. MCFPGA_INIT_N = 1 << 1,
  37. MCFPGA_PROGRAM_N = 1 << 2,
  38. MCFPGA_UPDATE_ENABLE_N = 1 << 3,
  39. MCFPGA_RESET_N = 1 << 4,
  40. };
  41. enum {
  42. GPIO_MDC = 1 << 14,
  43. GPIO_MDIO = 1 << 15,
  44. };
  45. uint mclink_fpgacount;
  46. struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  47. struct {
  48. u8 bus;
  49. u8 addr;
  50. } strider_fans[] = CONFIG_STRIDER_FANS;
  51. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  52. {
  53. int res;
  54. switch (fpga) {
  55. case 0:
  56. out_le16(reg, data);
  57. break;
  58. default:
  59. res = mclink_send(fpga - 1, regoff, data);
  60. if (res < 0) {
  61. printf("mclink_send reg %02lx data %04x returned %d\n",
  62. regoff, data, res);
  63. return res;
  64. }
  65. break;
  66. }
  67. return 0;
  68. }
  69. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  70. {
  71. int res;
  72. switch (fpga) {
  73. case 0:
  74. *data = in_le16(reg);
  75. break;
  76. default:
  77. if (fpga > mclink_fpgacount)
  78. return -EINVAL;
  79. res = mclink_receive(fpga - 1, regoff, data);
  80. if (res < 0) {
  81. printf("mclink_receive reg %02lx returned %d\n",
  82. regoff, res);
  83. return res;
  84. }
  85. }
  86. return 0;
  87. }
  88. int checkboard(void)
  89. {
  90. char *s = env_get("serial#");
  91. bool hw_type_cat = pca9698_get_value(0x20, 18);
  92. puts("Board: ");
  93. printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
  94. if (s) {
  95. puts(", serial# ");
  96. puts(s);
  97. }
  98. puts("\n");
  99. return 0;
  100. }
  101. int last_stage_init(void)
  102. {
  103. int slaves;
  104. uint k;
  105. uint mux_ch;
  106. uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
  107. #ifdef CONFIG_STRIDER_CPU
  108. uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
  109. #endif
  110. bool hw_type_cat = pca9698_get_value(0x20, 18);
  111. #ifdef CONFIG_STRIDER_CON_DP
  112. bool is_dh = pca9698_get_value(0x20, 25);
  113. #endif
  114. bool ch0_sgmii2_present;
  115. /* Turn on Analog Devices ADV7611 */
  116. pca9698_direction_output(0x20, 8, 0);
  117. /* Turn on Parade DP501 */
  118. pca9698_direction_output(0x20, 10, 1);
  119. pca9698_direction_output(0x20, 11, 1);
  120. ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
  121. /* wait for FPGA done, then reset FPGA */
  122. for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
  123. uint ctr = 0;
  124. uchar *mclink_controllers = mclink_controllers_dvi;
  125. #ifdef CONFIG_STRIDER_CPU
  126. if (i2c_probe(mclink_controllers[k])) {
  127. mclink_controllers = mclink_controllers_dp;
  128. if (i2c_probe(mclink_controllers[k]))
  129. continue;
  130. }
  131. #else
  132. if (i2c_probe(mclink_controllers[k]))
  133. continue;
  134. #endif
  135. while (!(pca953x_get_val(mclink_controllers[k])
  136. & MCFPGA_DONE)) {
  137. mdelay(100);
  138. if (ctr++ > 5) {
  139. printf("no done for mclink_controller %d\n", k);
  140. break;
  141. }
  142. }
  143. pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
  144. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
  145. udelay(10);
  146. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
  147. MCFPGA_RESET_N);
  148. }
  149. if (hw_type_cat) {
  150. int retval;
  151. struct mii_dev *mdiodev = mdio_alloc();
  152. if (!mdiodev)
  153. return -ENOMEM;
  154. strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
  155. mdiodev->read = bb_miiphy_read;
  156. mdiodev->write = bb_miiphy_write;
  157. retval = mdio_register(mdiodev);
  158. if (retval < 0)
  159. return retval;
  160. for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
  161. if ((mux_ch == 1) && !ch0_sgmii2_present)
  162. continue;
  163. setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
  164. }
  165. }
  166. /* give slave-PLLs and Parade DP501 some time to be up and running */
  167. mdelay(500);
  168. mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
  169. slaves = mclink_probe();
  170. mclink_fpgacount = 0;
  171. ioep_fpga_print_info(0);
  172. if (!adv7611_probe(0))
  173. printf(" Advantiv ADV7611 HDMI Receiver\n");
  174. #ifdef CONFIG_STRIDER_CON
  175. if (ioep_fpga_has_osd(0))
  176. osd_probe(0);
  177. #endif
  178. #ifdef CONFIG_STRIDER_CON_DP
  179. if (ioep_fpga_has_osd(0)) {
  180. osd_probe(0);
  181. if (is_dh)
  182. osd_probe(4);
  183. }
  184. #endif
  185. #ifdef CONFIG_STRIDER_CPU
  186. ch7301_probe(0, false);
  187. dp501_probe(0, false);
  188. #endif
  189. if (slaves <= 0)
  190. return 0;
  191. mclink_fpgacount = slaves;
  192. #ifdef CONFIG_STRIDER_CPU
  193. /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
  194. for (k = 1; k <= slaves; ++k)
  195. FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
  196. mdelay(500);
  197. #endif
  198. for (k = 1; k <= slaves; ++k) {
  199. ioep_fpga_print_info(k);
  200. #ifdef CONFIG_STRIDER_CON
  201. if (ioep_fpga_has_osd(k))
  202. osd_probe(k);
  203. #endif
  204. #ifdef CONFIG_STRIDER_CON_DP
  205. if (ioep_fpga_has_osd(k)) {
  206. osd_probe(k);
  207. if (is_dh)
  208. osd_probe(k + 4);
  209. }
  210. #endif
  211. #ifdef CONFIG_STRIDER_CPU
  212. if (!adv7611_probe(k))
  213. printf(" Advantiv ADV7611 HDMI Receiver\n");
  214. ch7301_probe(k, false);
  215. dp501_probe(k, false);
  216. #endif
  217. if (hw_type_cat) {
  218. int retval;
  219. struct mii_dev *mdiodev = mdio_alloc();
  220. if (!mdiodev)
  221. return -ENOMEM;
  222. strncpy(mdiodev->name, bb_miiphy_buses[k].name,
  223. MDIO_NAME_LEN);
  224. mdiodev->read = bb_miiphy_read;
  225. mdiodev->write = bb_miiphy_write;
  226. retval = mdio_register(mdiodev);
  227. if (retval < 0)
  228. return retval;
  229. setup_88e1514(bb_miiphy_buses[k].name, 0);
  230. }
  231. }
  232. for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
  233. i2c_set_bus_num(strider_fans[k].bus);
  234. init_fan_controller(strider_fans[k].addr);
  235. }
  236. return 0;
  237. }
  238. /*
  239. * provide access to fpga gpios (for I2C bitbang)
  240. * (these may look all too simple but make iocon.h much more readable)
  241. */
  242. void fpga_gpio_set(uint bus, int pin)
  243. {
  244. FPGA_SET_REG(bus, gpio.set, pin);
  245. }
  246. void fpga_gpio_clear(uint bus, int pin)
  247. {
  248. FPGA_SET_REG(bus, gpio.clear, pin);
  249. }
  250. int fpga_gpio_get(uint bus, int pin)
  251. {
  252. u16 val;
  253. FPGA_GET_REG(bus, gpio.read, &val);
  254. return val & pin;
  255. }
  256. #ifdef CONFIG_STRIDER_CON_DP
  257. void fpga_control_set(uint bus, int pin)
  258. {
  259. u16 val;
  260. FPGA_GET_REG(bus, control, &val);
  261. FPGA_SET_REG(bus, control, val | pin);
  262. }
  263. void fpga_control_clear(uint bus, int pin)
  264. {
  265. u16 val;
  266. FPGA_GET_REG(bus, control, &val);
  267. FPGA_SET_REG(bus, control, val & ~pin);
  268. }
  269. #endif
  270. void mpc8308_init(void)
  271. {
  272. pca9698_direction_output(0x20, 26, 1);
  273. }
  274. void mpc8308_set_fpga_reset(uint state)
  275. {
  276. pca9698_set_value(0x20, 26, state ? 0 : 1);
  277. }
  278. void mpc8308_setup_hw(void)
  279. {
  280. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  281. /*
  282. * set "startup-finished"-gpios
  283. */
  284. setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
  285. setbits_gpio0_out(BIT(31 - 12));
  286. }
  287. int mpc8308_get_fpga_done(uint fpga)
  288. {
  289. return pca9698_get_value(0x20, 20);
  290. }
  291. #ifdef CONFIG_FSL_ESDHC
  292. int board_mmc_init(bd_t *bd)
  293. {
  294. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  295. sysconf83xx_t *sysconf = &immr->sysconf;
  296. /* Enable cache snooping in eSDHC system configuration register */
  297. out_be32(&sysconf->sdhccr, 0x02000000);
  298. return fsl_esdhc_mmc_init(bd);
  299. }
  300. #endif
  301. static struct pci_region pcie_regions_0[] = {
  302. {
  303. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  304. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  305. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  306. .flags = PCI_REGION_MEM,
  307. },
  308. {
  309. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  310. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  311. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  312. .flags = PCI_REGION_IO,
  313. },
  314. };
  315. void pci_init_board(void)
  316. {
  317. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  318. sysconf83xx_t *sysconf = &immr->sysconf;
  319. law83xx_t *pcie_law = sysconf->pcielaw;
  320. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  321. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  322. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  323. /* Deassert the resets in the control register */
  324. out_be32(&sysconf->pecr1, 0xE0008000);
  325. udelay(2000);
  326. /* Configure PCI Express Local Access Windows */
  327. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  328. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  329. mpc83xx_pcie_init(1, pcie_reg);
  330. }
  331. ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  332. {
  333. info->portwidth = FLASH_CFI_16BIT;
  334. info->chipwidth = FLASH_CFI_BY16;
  335. info->interface = FLASH_CFI_X16;
  336. return 1;
  337. }
  338. #if defined(CONFIG_OF_BOARD_SETUP)
  339. int ft_board_setup(void *blob, bd_t *bd)
  340. {
  341. ft_cpu_setup(blob, bd);
  342. fsl_fdt_fixup_dr_usb(blob, bd);
  343. fdt_fixup_esdhc(blob, bd);
  344. return 0;
  345. }
  346. #endif
  347. /*
  348. * FPGA MII bitbang implementation
  349. */
  350. struct fpga_mii {
  351. uint fpga;
  352. int mdio;
  353. } fpga_mii[] = {
  354. { 0, 1},
  355. { 1, 1},
  356. { 2, 1},
  357. { 3, 1},
  358. };
  359. static int mii_dummy_init(struct bb_miiphy_bus *bus)
  360. {
  361. return 0;
  362. }
  363. static int mii_mdio_active(struct bb_miiphy_bus *bus)
  364. {
  365. struct fpga_mii *fpga_mii = bus->priv;
  366. if (fpga_mii->mdio)
  367. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  368. else
  369. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  370. return 0;
  371. }
  372. static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
  373. {
  374. struct fpga_mii *fpga_mii = bus->priv;
  375. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  376. return 0;
  377. }
  378. static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
  379. {
  380. struct fpga_mii *fpga_mii = bus->priv;
  381. if (v)
  382. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  383. else
  384. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  385. fpga_mii->mdio = v;
  386. return 0;
  387. }
  388. static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
  389. {
  390. u16 gpio;
  391. struct fpga_mii *fpga_mii = bus->priv;
  392. FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
  393. *v = ((gpio & GPIO_MDIO) != 0);
  394. return 0;
  395. }
  396. static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
  397. {
  398. struct fpga_mii *fpga_mii = bus->priv;
  399. if (v)
  400. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
  401. else
  402. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
  403. return 0;
  404. }
  405. static int mii_delay(struct bb_miiphy_bus *bus)
  406. {
  407. udelay(1);
  408. return 0;
  409. }
  410. struct bb_miiphy_bus bb_miiphy_buses[] = {
  411. {
  412. .name = "board0",
  413. .init = mii_dummy_init,
  414. .mdio_active = mii_mdio_active,
  415. .mdio_tristate = mii_mdio_tristate,
  416. .set_mdio = mii_set_mdio,
  417. .get_mdio = mii_get_mdio,
  418. .set_mdc = mii_set_mdc,
  419. .delay = mii_delay,
  420. .priv = &fpga_mii[0],
  421. },
  422. {
  423. .name = "board1",
  424. .init = mii_dummy_init,
  425. .mdio_active = mii_mdio_active,
  426. .mdio_tristate = mii_mdio_tristate,
  427. .set_mdio = mii_set_mdio,
  428. .get_mdio = mii_get_mdio,
  429. .set_mdc = mii_set_mdc,
  430. .delay = mii_delay,
  431. .priv = &fpga_mii[1],
  432. },
  433. {
  434. .name = "board2",
  435. .init = mii_dummy_init,
  436. .mdio_active = mii_mdio_active,
  437. .mdio_tristate = mii_mdio_tristate,
  438. .set_mdio = mii_set_mdio,
  439. .get_mdio = mii_get_mdio,
  440. .set_mdc = mii_set_mdc,
  441. .delay = mii_delay,
  442. .priv = &fpga_mii[2],
  443. },
  444. {
  445. .name = "board3",
  446. .init = mii_dummy_init,
  447. .mdio_active = mii_mdio_active,
  448. .mdio_tristate = mii_mdio_tristate,
  449. .set_mdio = mii_set_mdio,
  450. .get_mdio = mii_get_mdio,
  451. .set_mdc = mii_set_mdc,
  452. .delay = mii_delay,
  453. .priv = &fpga_mii[3],
  454. },
  455. };
  456. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);