mpc8308.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <init.h>
  9. #include <asm/processor.h>
  10. #include <asm/io.h>
  11. #include <asm/global_data.h>
  12. #include "mpc8308.h"
  13. #include <gdsys_fpga.h>
  14. #define REFLECTION_TESTPATTERN 0xdede
  15. #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  16. #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  17. #define REFLECTION_TESTREG reflection_low
  18. #else
  19. #define REFLECTION_TESTREG reflection_high
  20. #endif
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
  23. /* as gpio output status cannot be read back, we have to buffer it locally */
  24. u32 gpio0_out;
  25. void setbits_gpio0_out(u32 mask)
  26. {
  27. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  28. gpio0_out |= mask;
  29. out_be32(&immr->gpio[0].dat, gpio0_out);
  30. }
  31. void clrbits_gpio0_out(u32 mask)
  32. {
  33. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  34. gpio0_out &= ~mask;
  35. out_be32(&immr->gpio[0].dat, gpio0_out);
  36. }
  37. int get_fpga_state(uint dev)
  38. {
  39. return gd->arch.fpga_state[dev];
  40. }
  41. int board_early_init_f(void)
  42. {
  43. uint k;
  44. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  45. gd->arch.fpga_state[k] = 0;
  46. return 0;
  47. }
  48. int board_early_init_r(void)
  49. {
  50. uint k;
  51. uint ctr;
  52. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  53. gd->arch.fpga_state[k] = 0;
  54. /*
  55. * reset FPGA
  56. */
  57. mpc8308_init();
  58. mpc8308_set_fpga_reset(1);
  59. mpc8308_setup_hw();
  60. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  61. ctr = 0;
  62. while (!mpc8308_get_fpga_done(k)) {
  63. mdelay(100);
  64. if (ctr++ > 5) {
  65. gd->arch.fpga_state[k] |=
  66. FPGA_STATE_DONE_FAILED;
  67. break;
  68. }
  69. }
  70. }
  71. udelay(10);
  72. mpc8308_set_fpga_reset(0);
  73. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  74. /*
  75. * wait for fpga out of reset
  76. */
  77. ctr = 0;
  78. while (1) {
  79. u16 val;
  80. FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  81. FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
  82. if (val == REFLECTION_TESTPATTERN_INV)
  83. break;
  84. mdelay(100);
  85. if (ctr++ > 5) {
  86. gd->arch.fpga_state[k] |=
  87. FPGA_STATE_REFLECTION_FAILED;
  88. break;
  89. }
  90. }
  91. }
  92. return 0;
  93. }
  94. #endif