vf610twr.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/iomux-vf610.h>
  9. #include <asm/arch/ddrmc-vf610.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <mmc.h>
  13. #include <fsl_esdhc_imx.h>
  14. #include <miiphy.h>
  15. #include <netdev.h>
  16. #include <i2c.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  19. PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
  20. #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  21. PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
  22. #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
  23. PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
  24. static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
  25. /* levelling */
  26. { DDRMC_CR97_WRLVL_EN, 97 },
  27. { DDRMC_CR98_WRLVL_DL_0(0), 98 },
  28. { DDRMC_CR99_WRLVL_DL_1(0), 99 },
  29. { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
  30. { DDRMC_CR105_RDLVL_DL_0(0), 105 },
  31. { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
  32. { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
  33. /* AXI */
  34. { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
  35. { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  36. { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  37. DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  38. { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  39. DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  40. { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  41. DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  42. { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  43. DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  44. { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  45. { DDRMC_CR126_PHY_RDLAT(8), 126 },
  46. { DDRMC_CR132_WRLAT_ADJ(5) |
  47. DDRMC_CR132_RDLAT_ADJ(6), 132 },
  48. { DDRMC_CR137_PHYCTL_DL(2), 137 },
  49. { DDRMC_CR138_PHY_WRLV_MXDL(256) |
  50. DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
  51. { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  52. DDRMC_CR139_PHY_WRLV_DLL(3) |
  53. DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  54. { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
  55. { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
  56. DDRMC_CR143_RDLV_MXDL(128), 143 },
  57. { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
  58. DDRMC_CR144_PHY_RDLV_DLL(3) |
  59. DDRMC_CR144_PHY_RDLV_EN(3), 144 },
  60. { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
  61. { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
  62. { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
  63. { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
  64. { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
  65. DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
  66. { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  67. DDRMC_CR154_PAD_ZQ_MODE(1) |
  68. DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  69. DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
  70. { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
  71. { DDRMC_CR158_TWR(6), 158 },
  72. { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
  73. DDRMC_CR161_TODTH_WR(2), 161 },
  74. /* end marker */
  75. { 0, -1 }
  76. };
  77. int dram_init(void)
  78. {
  79. static const struct ddr3_jedec_timings timings = {
  80. .tinit = 5,
  81. .trst_pwron = 80000,
  82. .cke_inactive = 200000,
  83. .wrlat = 5,
  84. .caslat_lin = 12,
  85. .trc = 21,
  86. .trrd = 4,
  87. .tccd = 4,
  88. .tbst_int_interval = 0,
  89. .tfaw = 20,
  90. .trp = 6,
  91. .twtr = 4,
  92. .tras_min = 15,
  93. .tmrd = 4,
  94. .trtp = 4,
  95. .tras_max = 28080,
  96. .tmod = 12,
  97. .tckesr = 4,
  98. .tcke = 3,
  99. .trcd_int = 6,
  100. .tras_lockout = 0,
  101. .tdal = 12,
  102. .bstlen = 3,
  103. .tdll = 512,
  104. .trp_ab = 6,
  105. .tref = 3120,
  106. .trfc = 44,
  107. .tref_int = 0,
  108. .tpdex = 3,
  109. .txpdll = 10,
  110. .txsnr = 48,
  111. .txsr = 468,
  112. .cksrx = 5,
  113. .cksre = 5,
  114. .freq_chg_en = 0,
  115. .zqcl = 256,
  116. .zqinit = 512,
  117. .zqcs = 64,
  118. .ref_per_zq = 64,
  119. .zqcs_rotate = 0,
  120. .aprebit = 10,
  121. .cmd_age_cnt = 64,
  122. .age_cnt = 64,
  123. .q_fullness = 7,
  124. .odt_rd_mapcs0 = 0,
  125. .odt_wr_mapcs0 = 1,
  126. .wlmrd = 40,
  127. .wldqsen = 25,
  128. };
  129. ddrmc_setup_iomux(NULL, 0);
  130. ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
  131. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  132. return 0;
  133. }
  134. static void setup_iomux_uart(void)
  135. {
  136. static const iomux_v3_cfg_t uart1_pads[] = {
  137. NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
  138. NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
  139. };
  140. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  141. }
  142. static void setup_iomux_enet(void)
  143. {
  144. static const iomux_v3_cfg_t enet0_pads[] = {
  145. NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
  146. NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
  147. NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
  148. NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
  149. NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
  150. NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
  151. NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
  152. NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
  153. NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
  154. NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
  155. };
  156. imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
  157. }
  158. static void setup_iomux_i2c(void)
  159. {
  160. static const iomux_v3_cfg_t i2c0_pads[] = {
  161. VF610_PAD_PTB14__I2C0_SCL,
  162. VF610_PAD_PTB15__I2C0_SDA,
  163. };
  164. imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
  165. }
  166. #ifdef CONFIG_NAND_VF610_NFC
  167. static void setup_iomux_nfc(void)
  168. {
  169. static const iomux_v3_cfg_t nfc_pads[] = {
  170. VF610_PAD_PTD31__NF_IO15,
  171. VF610_PAD_PTD30__NF_IO14,
  172. VF610_PAD_PTD29__NF_IO13,
  173. VF610_PAD_PTD28__NF_IO12,
  174. VF610_PAD_PTD27__NF_IO11,
  175. VF610_PAD_PTD26__NF_IO10,
  176. VF610_PAD_PTD25__NF_IO9,
  177. VF610_PAD_PTD24__NF_IO8,
  178. VF610_PAD_PTD23__NF_IO7,
  179. VF610_PAD_PTD22__NF_IO6,
  180. VF610_PAD_PTD21__NF_IO5,
  181. VF610_PAD_PTD20__NF_IO4,
  182. VF610_PAD_PTD19__NF_IO3,
  183. VF610_PAD_PTD18__NF_IO2,
  184. VF610_PAD_PTD17__NF_IO1,
  185. VF610_PAD_PTD16__NF_IO0,
  186. VF610_PAD_PTB24__NF_WE_B,
  187. VF610_PAD_PTB25__NF_CE0_B,
  188. VF610_PAD_PTB27__NF_RE_B,
  189. VF610_PAD_PTC26__NF_RB_B,
  190. VF610_PAD_PTC27__NF_ALE,
  191. VF610_PAD_PTC28__NF_CLE
  192. };
  193. imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
  194. }
  195. #endif
  196. static void setup_iomux_qspi(void)
  197. {
  198. static const iomux_v3_cfg_t qspi0_pads[] = {
  199. VF610_PAD_PTD0__QSPI0_A_QSCK,
  200. VF610_PAD_PTD1__QSPI0_A_CS0,
  201. VF610_PAD_PTD2__QSPI0_A_DATA3,
  202. VF610_PAD_PTD3__QSPI0_A_DATA2,
  203. VF610_PAD_PTD4__QSPI0_A_DATA1,
  204. VF610_PAD_PTD5__QSPI0_A_DATA0,
  205. VF610_PAD_PTD7__QSPI0_B_QSCK,
  206. VF610_PAD_PTD8__QSPI0_B_CS0,
  207. VF610_PAD_PTD9__QSPI0_B_DATA3,
  208. VF610_PAD_PTD10__QSPI0_B_DATA2,
  209. VF610_PAD_PTD11__QSPI0_B_DATA1,
  210. VF610_PAD_PTD12__QSPI0_B_DATA0,
  211. };
  212. imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
  213. }
  214. #ifdef CONFIG_FSL_ESDHC_IMX
  215. struct fsl_esdhc_cfg esdhc_cfg[1] = {
  216. {ESDHC1_BASE_ADDR},
  217. };
  218. int board_mmc_getcd(struct mmc *mmc)
  219. {
  220. /* eSDHC1 is always present */
  221. return 1;
  222. }
  223. int board_mmc_init(bd_t *bis)
  224. {
  225. static const iomux_v3_cfg_t esdhc1_pads[] = {
  226. NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
  227. NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
  228. NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
  229. NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
  230. NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
  231. NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
  232. };
  233. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  234. imx_iomux_v3_setup_multiple_pads(
  235. esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
  236. return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
  237. }
  238. #endif
  239. static void clock_init(void)
  240. {
  241. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  242. struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
  243. clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
  244. CCM_CCGR0_UART1_CTRL_MASK);
  245. clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
  246. CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
  247. clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
  248. CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
  249. CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
  250. CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
  251. CCM_CCGR2_QSPI0_CTRL_MASK);
  252. clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
  253. CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
  254. clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
  255. CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
  256. CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
  257. clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
  258. CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
  259. clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
  260. CCM_CCGR7_SDHC1_CTRL_MASK);
  261. clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
  262. CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
  263. clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
  264. CCM_CCGR10_NFC_CTRL_MASK);
  265. clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
  266. ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
  267. clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
  268. ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
  269. clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
  270. CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
  271. clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
  272. CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
  273. CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
  274. CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
  275. CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
  276. CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
  277. CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
  278. clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
  279. CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
  280. CCM_CACRR_ARM_CLK_DIV(0));
  281. clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
  282. CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
  283. CCM_CSCMR1_NFC_CLK_SEL(0));
  284. clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
  285. CCM_CSCDR1_RMII_CLK_EN);
  286. clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
  287. CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
  288. CCM_CSCDR2_NFC_EN);
  289. clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
  290. CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
  291. CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
  292. CCM_CSCDR3_NFC_PRE_DIV(5));
  293. clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
  294. CCM_CSCMR2_RMII_CLK_SEL(0));
  295. }
  296. static void mscm_init(void)
  297. {
  298. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
  299. int i;
  300. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  301. writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
  302. }
  303. int board_phy_config(struct phy_device *phydev)
  304. {
  305. if (phydev->drv->config)
  306. phydev->drv->config(phydev);
  307. return 0;
  308. }
  309. int board_early_init_f(void)
  310. {
  311. clock_init();
  312. mscm_init();
  313. setup_iomux_uart();
  314. setup_iomux_enet();
  315. setup_iomux_i2c();
  316. setup_iomux_qspi();
  317. #ifdef CONFIG_NAND_VF610_NFC
  318. setup_iomux_nfc();
  319. #endif
  320. return 0;
  321. }
  322. int board_init(void)
  323. {
  324. struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
  325. /* address of boot parameters */
  326. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  327. /*
  328. * Enable external 32K Oscillator
  329. *
  330. * The internal clock experiences significant drift
  331. * so we must use the external oscillator in order
  332. * to maintain correct time in the hwclock
  333. */
  334. setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
  335. return 0;
  336. }
  337. int checkboard(void)
  338. {
  339. puts("Board: vf610twr\n");
  340. return 0;
  341. }