t208xqds_qixis.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __T208xQDS_QIXIS_H__
  6. #define __T208xQDS_QIXIS_H__
  7. /* Definitions of QIXIS Registers for T208xQDS */
  8. #define QIXIS_SRDS1CLK_122 0x5a
  9. #define QIXIS_SRDS1CLK_125 0x5e
  10. /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
  11. #define BRDCFG4_EMISEL_MASK 0xE0
  12. #define BRDCFG4_EMISEL_SHIFT 5
  13. /* SYSCLK */
  14. #define QIXIS_SYSCLK_66 0x0
  15. #define QIXIS_SYSCLK_83 0x1
  16. #define QIXIS_SYSCLK_100 0x2
  17. #define QIXIS_SYSCLK_125 0x3
  18. #define QIXIS_SYSCLK_133 0x4
  19. #define QIXIS_SYSCLK_150 0x5
  20. #define QIXIS_SYSCLK_160 0x6
  21. #define QIXIS_SYSCLK_166 0x7
  22. /* DDRCLK */
  23. #define QIXIS_DDRCLK_66 0x0
  24. #define QIXIS_DDRCLK_100 0x1
  25. #define QIXIS_DDRCLK_125 0x2
  26. #define QIXIS_DDRCLK_133 0x3
  27. #define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
  28. #define BRDCFG9_SFP_TX_EN 0x10
  29. #define BRDCFG12_SD3EN_MASK 0x20
  30. #define BRDCFG12_SD3MX_MASK 0x08
  31. #define BRDCFG12_SD3MX_SLOT5 0x08
  32. #define BRDCFG12_SD3MX_SLOT6 0x00
  33. #define BRDCFG12_SD4EN_MASK 0x04
  34. #define BRDCFG12_SD4MX_MASK 0x03
  35. #define BRDCFG12_SD4MX_SLOT7 0x02
  36. #define BRDCFG12_SD4MX_SLOT8 0x01
  37. #define BRDCFG12_SD4MX_AURO_SATA 0x00
  38. #endif