eth_t208xqds.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. *
  5. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <netdev.h>
  10. #include <asm/mmu.h>
  11. #include <asm/processor.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/fsl_law.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/fsl_portals.h>
  16. #include <asm/fsl_liodn.h>
  17. #include <malloc.h>
  18. #include <fm_eth.h>
  19. #include <fsl_mdio.h>
  20. #include <miiphy.h>
  21. #include <phy.h>
  22. #include <fsl_dtsec.h>
  23. #include <asm/fsl_serdes.h>
  24. #include <hwconfig.h>
  25. #include "../common/qixis.h"
  26. #include "../common/fman.h"
  27. #include "t208xqds_qixis.h"
  28. #define EMI_NONE 0xFFFFFFFF
  29. #define EMI1_RGMII1 0
  30. #define EMI1_RGMII2 1
  31. #define EMI1_SLOT1 2
  32. #if defined(CONFIG_TARGET_T2080QDS)
  33. #define EMI1_SLOT2 6
  34. #define EMI1_SLOT3 3
  35. #define EMI1_SLOT4 4
  36. #define EMI1_SLOT5 5
  37. #define EMI2 7
  38. #elif defined(CONFIG_TARGET_T2081QDS)
  39. #define EMI1_SLOT2 3
  40. #define EMI1_SLOT3 4
  41. #define EMI1_SLOT5 5
  42. #define EMI1_SLOT6 6
  43. #define EMI1_SLOT7 7
  44. #define EMI2 8
  45. #endif
  46. #define PCCR1_SGMIIA_KX_MASK 0x00008000
  47. #define PCCR1_SGMIIB_KX_MASK 0x00004000
  48. #define PCCR1_SGMIIC_KX_MASK 0x00002000
  49. #define PCCR1_SGMIID_KX_MASK 0x00001000
  50. #define PCCR1_SGMIIE_KX_MASK 0x00000800
  51. #define PCCR1_SGMIIF_KX_MASK 0x00000400
  52. #define PCCR1_SGMIIG_KX_MASK 0x00000200
  53. #define PCCR1_SGMIIH_KX_MASK 0x00000100
  54. static int mdio_mux[NUM_FM_PORTS];
  55. static const char * const mdio_names[] = {
  56. #if defined(CONFIG_TARGET_T2080QDS)
  57. "T2080QDS_MDIO_RGMII1",
  58. "T2080QDS_MDIO_RGMII2",
  59. "T2080QDS_MDIO_SLOT1",
  60. "T2080QDS_MDIO_SLOT3",
  61. "T2080QDS_MDIO_SLOT4",
  62. "T2080QDS_MDIO_SLOT5",
  63. "T2080QDS_MDIO_SLOT2",
  64. "T2080QDS_MDIO_10GC",
  65. #elif defined(CONFIG_TARGET_T2081QDS)
  66. "T2081QDS_MDIO_RGMII1",
  67. "T2081QDS_MDIO_RGMII2",
  68. "T2081QDS_MDIO_SLOT1",
  69. "T2081QDS_MDIO_SLOT2",
  70. "T2081QDS_MDIO_SLOT3",
  71. "T2081QDS_MDIO_SLOT5",
  72. "T2081QDS_MDIO_SLOT6",
  73. "T2081QDS_MDIO_SLOT7",
  74. "T2081QDS_MDIO_10GC",
  75. #endif
  76. };
  77. /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
  78. #if defined(CONFIG_TARGET_T2080QDS)
  79. static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
  80. #elif defined(CONFIG_TARGET_T2081QDS)
  81. static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
  82. #endif
  83. static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
  84. {
  85. return mdio_names[muxval];
  86. }
  87. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  88. {
  89. struct mii_dev *bus;
  90. const char *name = t208xqds_mdio_name_for_muxval(muxval);
  91. if (!name) {
  92. printf("No bus for muxval %x\n", muxval);
  93. return NULL;
  94. }
  95. bus = miiphy_get_dev_by_name(name);
  96. if (!bus) {
  97. printf("No bus by name %s\n", name);
  98. return NULL;
  99. }
  100. return bus;
  101. }
  102. struct t208xqds_mdio {
  103. u8 muxval;
  104. struct mii_dev *realbus;
  105. };
  106. static void t208xqds_mux_mdio(u8 muxval)
  107. {
  108. u8 brdcfg4;
  109. if (muxval < 8) {
  110. brdcfg4 = QIXIS_READ(brdcfg[4]);
  111. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  112. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  113. QIXIS_WRITE(brdcfg[4], brdcfg4);
  114. }
  115. }
  116. static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  117. int regnum)
  118. {
  119. struct t208xqds_mdio *priv = bus->priv;
  120. t208xqds_mux_mdio(priv->muxval);
  121. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  122. }
  123. static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  124. int regnum, u16 value)
  125. {
  126. struct t208xqds_mdio *priv = bus->priv;
  127. t208xqds_mux_mdio(priv->muxval);
  128. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  129. }
  130. static int t208xqds_mdio_reset(struct mii_dev *bus)
  131. {
  132. struct t208xqds_mdio *priv = bus->priv;
  133. return priv->realbus->reset(priv->realbus);
  134. }
  135. static int t208xqds_mdio_init(char *realbusname, u8 muxval)
  136. {
  137. struct t208xqds_mdio *pmdio;
  138. struct mii_dev *bus = mdio_alloc();
  139. if (!bus) {
  140. printf("Failed to allocate t208xqds MDIO bus\n");
  141. return -1;
  142. }
  143. pmdio = malloc(sizeof(*pmdio));
  144. if (!pmdio) {
  145. printf("Failed to allocate t208xqds private data\n");
  146. free(bus);
  147. return -1;
  148. }
  149. bus->read = t208xqds_mdio_read;
  150. bus->write = t208xqds_mdio_write;
  151. bus->reset = t208xqds_mdio_reset;
  152. strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));
  153. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  154. if (!pmdio->realbus) {
  155. printf("No bus with name %s\n", realbusname);
  156. free(bus);
  157. free(pmdio);
  158. return -1;
  159. }
  160. pmdio->muxval = muxval;
  161. bus->priv = pmdio;
  162. return mdio_register(bus);
  163. }
  164. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  165. enum fm_port port, int offset)
  166. {
  167. int phy;
  168. char alias[20];
  169. char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
  170. char buf[32] = "serdes-1,";
  171. struct fixed_link f_link;
  172. int media_type = 0;
  173. int off;
  174. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  175. #ifdef CONFIG_TARGET_T2080QDS
  176. serdes_corenet_t *srds_regs =
  177. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  178. u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
  179. #endif
  180. u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  181. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  182. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  183. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  184. phy = fm_info_get_phy_address(port);
  185. switch (port) {
  186. #if defined(CONFIG_TARGET_T2080QDS)
  187. case FM1_DTSEC1:
  188. if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
  189. media_type = 1;
  190. fdt_set_phy_handle(fdt, compat, addr,
  191. "phy_1gkx1");
  192. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
  193. sprintf(buf, "%s%s%s", buf, "lane-c,",
  194. (char *)lane_mode[0]);
  195. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  196. PCCR1_SGMIIH_KX_MASK);
  197. break;
  198. }
  199. case FM1_DTSEC2:
  200. if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
  201. media_type = 1;
  202. fdt_set_phy_handle(fdt, compat, addr,
  203. "phy_1gkx2");
  204. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
  205. sprintf(buf, "%s%s%s", buf, "lane-d,",
  206. (char *)lane_mode[0]);
  207. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  208. PCCR1_SGMIIG_KX_MASK);
  209. break;
  210. }
  211. case FM1_DTSEC9:
  212. if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
  213. media_type = 1;
  214. fdt_set_phy_handle(fdt, compat, addr,
  215. "phy_1gkx9");
  216. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
  217. sprintf(buf, "%s%s%s", buf, "lane-a,",
  218. (char *)lane_mode[0]);
  219. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  220. PCCR1_SGMIIE_KX_MASK);
  221. break;
  222. }
  223. case FM1_DTSEC10:
  224. if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
  225. media_type = 1;
  226. fdt_set_phy_handle(fdt, compat, addr,
  227. "phy_1gkx10");
  228. fdt_status_okay_by_alias(fdt,
  229. "1gkx_pcs_mdio10");
  230. sprintf(buf, "%s%s%s", buf, "lane-b,",
  231. (char *)lane_mode[0]);
  232. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  233. PCCR1_SGMIIF_KX_MASK);
  234. break;
  235. }
  236. if (mdio_mux[port] == EMI1_SLOT2) {
  237. sprintf(alias, "phy_sgmii_s2_%x", phy);
  238. fdt_set_phy_handle(fdt, compat, addr, alias);
  239. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  240. } else if (mdio_mux[port] == EMI1_SLOT3) {
  241. sprintf(alias, "phy_sgmii_s3_%x", phy);
  242. fdt_set_phy_handle(fdt, compat, addr, alias);
  243. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  244. }
  245. break;
  246. case FM1_DTSEC5:
  247. if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
  248. media_type = 1;
  249. fdt_set_phy_handle(fdt, compat, addr,
  250. "phy_1gkx5");
  251. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
  252. sprintf(buf, "%s%s%s", buf, "lane-g,",
  253. (char *)lane_mode[0]);
  254. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  255. PCCR1_SGMIIC_KX_MASK);
  256. break;
  257. }
  258. case FM1_DTSEC6:
  259. if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
  260. media_type = 1;
  261. fdt_set_phy_handle(fdt, compat, addr,
  262. "phy_1gkx6");
  263. fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
  264. sprintf(buf, "%s%s%s", buf, "lane-h,",
  265. (char *)lane_mode[0]);
  266. out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
  267. PCCR1_SGMIID_KX_MASK);
  268. break;
  269. }
  270. if (mdio_mux[port] == EMI1_SLOT1) {
  271. sprintf(alias, "phy_sgmii_s1_%x", phy);
  272. fdt_set_phy_handle(fdt, compat, addr, alias);
  273. fdt_status_okay_by_alias(fdt, "emi1_slot1");
  274. } else if (mdio_mux[port] == EMI1_SLOT2) {
  275. sprintf(alias, "phy_sgmii_s2_%x", phy);
  276. fdt_set_phy_handle(fdt, compat, addr, alias);
  277. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  278. }
  279. break;
  280. #elif defined(CONFIG_TARGET_T2081QDS)
  281. case FM1_DTSEC1:
  282. case FM1_DTSEC2:
  283. case FM1_DTSEC5:
  284. case FM1_DTSEC6:
  285. case FM1_DTSEC9:
  286. case FM1_DTSEC10:
  287. if (mdio_mux[port] == EMI1_SLOT2) {
  288. sprintf(alias, "phy_sgmii_s2_%x", phy);
  289. fdt_set_phy_handle(fdt, compat, addr, alias);
  290. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  291. } else if (mdio_mux[port] == EMI1_SLOT3) {
  292. sprintf(alias, "phy_sgmii_s3_%x", phy);
  293. fdt_set_phy_handle(fdt, compat, addr, alias);
  294. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  295. } else if (mdio_mux[port] == EMI1_SLOT5) {
  296. sprintf(alias, "phy_sgmii_s5_%x", phy);
  297. fdt_set_phy_handle(fdt, compat, addr, alias);
  298. fdt_status_okay_by_alias(fdt, "emi1_slot5");
  299. } else if (mdio_mux[port] == EMI1_SLOT6) {
  300. sprintf(alias, "phy_sgmii_s6_%x", phy);
  301. fdt_set_phy_handle(fdt, compat, addr, alias);
  302. fdt_status_okay_by_alias(fdt, "emi1_slot6");
  303. } else if (mdio_mux[port] == EMI1_SLOT7) {
  304. sprintf(alias, "phy_sgmii_s7_%x", phy);
  305. fdt_set_phy_handle(fdt, compat, addr, alias);
  306. fdt_status_okay_by_alias(fdt, "emi1_slot7");
  307. }
  308. break;
  309. #endif
  310. default:
  311. break;
  312. }
  313. if (media_type) {
  314. /* set property for 1000BASE-KX in dtb */
  315. off = fdt_node_offset_by_compat_reg(fdt,
  316. "fsl,fman-memac-mdio", addr + 0x1000);
  317. fdt_setprop_string(fdt, off, "lane-instance", buf);
  318. }
  319. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
  320. switch (srds_s1) {
  321. case 0x66: /* XFI interface */
  322. case 0x6b:
  323. case 0x6c:
  324. case 0x6d:
  325. case 0x71:
  326. /*
  327. * if the 10G is XFI, check hwconfig to see what is the
  328. * media type, there are two types, fiber or copper,
  329. * fix the dtb accordingly.
  330. */
  331. switch (port) {
  332. case FM1_10GEC1:
  333. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
  334. /* it's MAC9 */
  335. media_type = 1;
  336. fdt_set_phy_handle(fdt, compat, addr,
  337. "phy_xfi9");
  338. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
  339. sprintf(buf, "%s%s%s", buf, "lane-a,",
  340. (char *)lane_mode[1]);
  341. }
  342. break;
  343. case FM1_10GEC2:
  344. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
  345. /* it's MAC10 */
  346. media_type = 1;
  347. fdt_set_phy_handle(fdt, compat, addr,
  348. "phy_xfi10");
  349. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
  350. sprintf(buf, "%s%s%s", buf, "lane-b,",
  351. (char *)lane_mode[1]);
  352. }
  353. break;
  354. case FM1_10GEC3:
  355. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
  356. /* it's MAC1 */
  357. media_type = 1;
  358. fdt_set_phy_handle(fdt, compat, addr,
  359. "phy_xfi1");
  360. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
  361. sprintf(buf, "%s%s%s", buf, "lane-c,",
  362. (char *)lane_mode[1]);
  363. }
  364. break;
  365. case FM1_10GEC4:
  366. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
  367. /* it's MAC2 */
  368. media_type = 1;
  369. fdt_set_phy_handle(fdt, compat, addr,
  370. "phy_xfi2");
  371. fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
  372. sprintf(buf, "%s%s%s", buf, "lane-d,",
  373. (char *)lane_mode[1]);
  374. }
  375. break;
  376. default:
  377. return;
  378. }
  379. if (!media_type) {
  380. /* fixed-link is used for XFI fiber cable */
  381. f_link.phy_id = port;
  382. f_link.duplex = 1;
  383. f_link.link_speed = 10000;
  384. f_link.pause = 0;
  385. f_link.asym_pause = 0;
  386. fdt_delprop(fdt, offset, "phy-handle");
  387. fdt_setprop(fdt, offset, "fixed-link", &f_link,
  388. sizeof(f_link));
  389. } else {
  390. /* set property for copper cable */
  391. off = fdt_node_offset_by_compat_reg(fdt,
  392. "fsl,fman-memac-mdio", addr + 0x1000);
  393. fdt_setprop_string(fdt, off,
  394. "lane-instance", buf);
  395. }
  396. break;
  397. default:
  398. break;
  399. }
  400. }
  401. }
  402. void fdt_fixup_board_enet(void *fdt)
  403. {
  404. return;
  405. }
  406. /*
  407. * This function reads RCW to check if Serdes1{A:H} is configured
  408. * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
  409. */
  410. static void initialize_lane_to_slot(void)
  411. {
  412. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  413. u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
  414. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  415. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  416. switch (srds_s1) {
  417. #if defined(CONFIG_TARGET_T2080QDS)
  418. case 0x51:
  419. case 0x5f:
  420. case 0x65:
  421. case 0x6b:
  422. case 0x71:
  423. lane_to_slot[5] = 2;
  424. lane_to_slot[6] = 2;
  425. lane_to_slot[7] = 2;
  426. break;
  427. case 0xa6:
  428. case 0x8e:
  429. case 0x8f:
  430. case 0x82:
  431. case 0x83:
  432. case 0xd3:
  433. case 0xd9:
  434. case 0xcb:
  435. lane_to_slot[6] = 2;
  436. lane_to_slot[7] = 2;
  437. break;
  438. case 0xda:
  439. lane_to_slot[4] = 3;
  440. lane_to_slot[5] = 3;
  441. lane_to_slot[6] = 3;
  442. lane_to_slot[7] = 3;
  443. break;
  444. #elif defined(CONFIG_TARGET_T2081QDS)
  445. case 0x6b:
  446. lane_to_slot[4] = 1;
  447. lane_to_slot[5] = 3;
  448. lane_to_slot[6] = 3;
  449. lane_to_slot[7] = 3;
  450. break;
  451. case 0xca:
  452. case 0xcb:
  453. lane_to_slot[1] = 7;
  454. lane_to_slot[2] = 6;
  455. lane_to_slot[3] = 5;
  456. lane_to_slot[5] = 3;
  457. lane_to_slot[6] = 3;
  458. lane_to_slot[7] = 3;
  459. break;
  460. case 0xf2:
  461. lane_to_slot[1] = 7;
  462. lane_to_slot[2] = 7;
  463. lane_to_slot[3] = 7;
  464. lane_to_slot[5] = 4;
  465. lane_to_slot[6] = 3;
  466. lane_to_slot[7] = 7;
  467. break;
  468. #endif
  469. default:
  470. break;
  471. }
  472. }
  473. int board_eth_init(bd_t *bis)
  474. {
  475. #if defined(CONFIG_FMAN_ENET)
  476. int i, idx, lane, slot, interface;
  477. struct memac_mdio_info dtsec_mdio_info;
  478. struct memac_mdio_info tgec_mdio_info;
  479. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  480. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  481. u32 srds_s1;
  482. srds_s1 = in_be32(&gur->rcwsr[4]) &
  483. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  484. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  485. initialize_lane_to_slot();
  486. /* Initialize the mdio_mux array so we can recognize empty elements */
  487. for (i = 0; i < NUM_FM_PORTS; i++)
  488. mdio_mux[i] = EMI_NONE;
  489. dtsec_mdio_info.regs =
  490. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  491. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  492. /* Register the 1G MDIO bus */
  493. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  494. tgec_mdio_info.regs =
  495. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  496. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  497. /* Register the 10G MDIO bus */
  498. fm_memac_mdio_init(bis, &tgec_mdio_info);
  499. /* Register the muxing front-ends to the MDIO buses */
  500. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  501. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  502. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  503. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  504. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  505. #if defined(CONFIG_TARGET_T2080QDS)
  506. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  507. #endif
  508. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  509. #if defined(CONFIG_TARGET_T2081QDS)
  510. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
  511. t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  512. #endif
  513. t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  514. /* Set the two on-board RGMII PHY address */
  515. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  516. if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  517. FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
  518. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  519. else
  520. fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
  521. switch (srds_s1) {
  522. case 0x1b:
  523. case 0x1c:
  524. case 0x95:
  525. case 0xa2:
  526. case 0x94:
  527. /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
  528. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  529. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  530. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  531. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  532. /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
  533. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  534. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  535. break;
  536. case 0x50:
  537. case 0x51:
  538. case 0x5e:
  539. case 0x5f:
  540. case 0x64:
  541. case 0x65:
  542. /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
  543. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  544. /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  545. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  546. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  547. break;
  548. case 0x66:
  549. case 0x67:
  550. /*
  551. * XFI does not need a PHY to work, but to avoid U-Boot use
  552. * default PHY address which is zero to a MAC when it found
  553. * a MAC has no PHY address, we give a PHY address to XFI
  554. * MAC, and should not use a real XAUI PHY address, since
  555. * MDIO can access it successfully, and then MDIO thinks
  556. * the XAUI card is used for the XFI MAC, which will cause
  557. * error.
  558. */
  559. fm_info_set_phy_address(FM1_10GEC1, 4);
  560. fm_info_set_phy_address(FM1_10GEC2, 5);
  561. fm_info_set_phy_address(FM1_10GEC3, 6);
  562. fm_info_set_phy_address(FM1_10GEC4, 7);
  563. break;
  564. case 0x6a:
  565. case 0x6b:
  566. fm_info_set_phy_address(FM1_10GEC1, 4);
  567. fm_info_set_phy_address(FM1_10GEC2, 5);
  568. fm_info_set_phy_address(FM1_10GEC3, 6);
  569. fm_info_set_phy_address(FM1_10GEC4, 7);
  570. /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
  571. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  572. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  573. break;
  574. case 0x6c:
  575. case 0x6d:
  576. fm_info_set_phy_address(FM1_10GEC1, 4);
  577. fm_info_set_phy_address(FM1_10GEC2, 5);
  578. /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
  579. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  580. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  581. break;
  582. case 0x70:
  583. case 0x71:
  584. /* SGMII in Slot3 */
  585. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  586. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  587. /* SGMII in Slot2 */
  588. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  589. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  590. break;
  591. case 0xa6:
  592. case 0x8e:
  593. case 0x8f:
  594. case 0x82:
  595. case 0x83:
  596. /* SGMII in Slot3 */
  597. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  598. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  599. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  600. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  601. /* SGMII in Slot2 */
  602. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  603. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  604. break;
  605. case 0xa4:
  606. case 0x96:
  607. case 0x8a:
  608. /* SGMII in Slot3 */
  609. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  610. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  611. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  612. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  613. break;
  614. #if defined(CONFIG_TARGET_T2080QDS)
  615. case 0xd9:
  616. case 0xd3:
  617. case 0xcb:
  618. /* SGMII in Slot3 */
  619. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
  620. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
  621. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
  622. /* SGMII in Slot2 */
  623. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
  624. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  625. break;
  626. #elif defined(CONFIG_TARGET_T2081QDS)
  627. case 0xca:
  628. case 0xcb:
  629. /* SGMII in Slot3 */
  630. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  631. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  632. /* SGMII in Slot5 */
  633. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  634. /* SGMII in Slot6 */
  635. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  636. /* SGMII in Slot7 */
  637. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  638. break;
  639. #endif
  640. case 0xf2:
  641. /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
  642. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  643. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  644. fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  645. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
  646. break;
  647. default:
  648. break;
  649. }
  650. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  651. idx = i - FM1_DTSEC1;
  652. interface = fm_info_get_enet_if(i);
  653. switch (interface) {
  654. case PHY_INTERFACE_MODE_SGMII:
  655. lane = serdes_get_first_lane(FSL_SRDS_1,
  656. SGMII_FM1_DTSEC1 + idx);
  657. if (lane < 0)
  658. break;
  659. slot = lane_to_slot[lane];
  660. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  661. idx + 1, slot);
  662. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  663. fm_disable_port(i);
  664. switch (slot) {
  665. case 1:
  666. mdio_mux[i] = EMI1_SLOT1;
  667. fm_info_set_mdio(i, mii_dev_for_muxval(
  668. mdio_mux[i]));
  669. break;
  670. case 2:
  671. mdio_mux[i] = EMI1_SLOT2;
  672. fm_info_set_mdio(i, mii_dev_for_muxval(
  673. mdio_mux[i]));
  674. break;
  675. case 3:
  676. mdio_mux[i] = EMI1_SLOT3;
  677. fm_info_set_mdio(i, mii_dev_for_muxval(
  678. mdio_mux[i]));
  679. break;
  680. #if defined(CONFIG_TARGET_T2081QDS)
  681. case 5:
  682. mdio_mux[i] = EMI1_SLOT5;
  683. fm_info_set_mdio(i, mii_dev_for_muxval(
  684. mdio_mux[i]));
  685. break;
  686. case 6:
  687. mdio_mux[i] = EMI1_SLOT6;
  688. fm_info_set_mdio(i, mii_dev_for_muxval(
  689. mdio_mux[i]));
  690. break;
  691. case 7:
  692. mdio_mux[i] = EMI1_SLOT7;
  693. fm_info_set_mdio(i, mii_dev_for_muxval(
  694. mdio_mux[i]));
  695. break;
  696. #endif
  697. }
  698. break;
  699. case PHY_INTERFACE_MODE_RGMII:
  700. if (i == FM1_DTSEC3)
  701. mdio_mux[i] = EMI1_RGMII1;
  702. else if (i == FM1_DTSEC4 || FM1_DTSEC10)
  703. mdio_mux[i] = EMI1_RGMII2;
  704. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  705. break;
  706. default:
  707. break;
  708. }
  709. }
  710. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  711. idx = i - FM1_10GEC1;
  712. switch (fm_info_get_enet_if(i)) {
  713. case PHY_INTERFACE_MODE_XGMII:
  714. if (srds_s1 == 0x51) {
  715. lane = serdes_get_first_lane(FSL_SRDS_1,
  716. XAUI_FM1_MAC9 + idx);
  717. } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
  718. lane = serdes_get_first_lane(FSL_SRDS_1,
  719. HIGIG_FM1_MAC9 + idx);
  720. } else {
  721. if (i == FM1_10GEC1 || i == FM1_10GEC2)
  722. lane = serdes_get_first_lane(FSL_SRDS_1,
  723. XFI_FM1_MAC9 + idx);
  724. else
  725. lane = serdes_get_first_lane(FSL_SRDS_1,
  726. XFI_FM1_MAC1 + idx);
  727. }
  728. if (lane < 0)
  729. break;
  730. mdio_mux[i] = EMI2;
  731. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  732. if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
  733. (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
  734. (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
  735. (srds_s1 == 0x71)) {
  736. /* As XFI is in cage intead of a slot, so
  737. * ensure doesn't disable the corresponding port
  738. */
  739. break;
  740. }
  741. slot = lane_to_slot[lane];
  742. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  743. fm_disable_port(i);
  744. break;
  745. default:
  746. break;
  747. }
  748. }
  749. cpu_eth_init(bis);
  750. #endif /* CONFIG_FMAN_ENET */
  751. return pci_eth_init(bis);
  752. }