tlb.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. struct fsl_e_tlb_entry tlb_table[] = {
  8. /* TLB 0 - for temp stack in cache */
  9. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  10. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  11. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  12. 0, 0, BOOKE_PAGESZ_4K, 0),
  13. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  14. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  15. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16. 0, 0, BOOKE_PAGESZ_4K, 0),
  17. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  18. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  23. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  24. 0, 0, BOOKE_PAGESZ_4K, 0),
  25. /* TLB 1 */
  26. /* *I*** - Covers boot page */
  27. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  28. /*
  29. * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
  30. * SRAM is at 0xfffc0000, it covered the 0xfffff000.
  31. */
  32. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  33. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  34. 0, 0, BOOKE_PAGESZ_256K, 1),
  35. #else
  36. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  37. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38. 0, 0, BOOKE_PAGESZ_4K, 1),
  39. #endif
  40. /* *I*G* - CCSRBAR */
  41. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  42. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  43. 0, 1, BOOKE_PAGESZ_16M, 1),
  44. /* *I*G* - Flash, localbus */
  45. /* This will be changed to *I*G* after relocation to RAM. */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  47. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  48. 0, 2, BOOKE_PAGESZ_256M, 1),
  49. /* *I*G* - PCI */
  50. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  51. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  52. 0, 3, BOOKE_PAGESZ_1G, 1),
  53. /* *I*G* - PCI I/O */
  54. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  55. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56. 0, 4, BOOKE_PAGESZ_256K, 1),
  57. /* Bman/Qman */
  58. #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  59. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  60. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  61. 0, 5, BOOKE_PAGESZ_16M, 1),
  62. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  63. CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  64. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65. 0, 6, BOOKE_PAGESZ_16M, 1),
  66. #endif
  67. #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  68. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  69. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  70. 0, 7, BOOKE_PAGESZ_16M, 1),
  71. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  72. CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  73. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  74. 0, 8, BOOKE_PAGESZ_16M, 1),
  75. #endif
  76. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  77. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  78. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  79. 0, 9, BOOKE_PAGESZ_4M, 1),
  80. #endif
  81. #ifdef CONFIG_SYS_NAND_BASE
  82. /*
  83. * *I*G - NAND
  84. * entry 14 and 15 has been used hard coded, they will be disabled
  85. * in cpu_init_f, so we use entry 16 for nand.
  86. */
  87. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  88. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89. 0, 10, BOOKE_PAGESZ_64K, 1),
  90. #endif
  91. #ifdef QIXIS_BASE
  92. SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
  93. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  94. 0, 11, BOOKE_PAGESZ_4K, 1),
  95. #endif
  96. };
  97. int num_tlb_entries = ARRAY_SIZE(tlb_table);