eth.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * The RGMII PHYs are provided by the two on-board PHY connected to
  7. * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
  8. * PHY or by the standard four-port SGMII riser card (VSC).
  9. */
  10. #include <common.h>
  11. #include <netdev.h>
  12. #include <asm/fsl_serdes.h>
  13. #include <asm/immap_85xx.h>
  14. #include <fm_eth.h>
  15. #include <fsl_mdio.h>
  16. #include <malloc.h>
  17. #include <fsl_dtsec.h>
  18. #include <vsc9953.h>
  19. #include "../common/fman.h"
  20. #include "../common/qixis.h"
  21. #include "t1040qds_qixis.h"
  22. #ifdef CONFIG_FMAN_ENET
  23. /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
  24. * Bank 1 -> Lanes A, B, C, D
  25. * Bank 2 -> Lanes E, F, G, H
  26. */
  27. /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
  28. * means that the mapping must be determined dynamically, or that the lane
  29. * maps to something other than a board slot.
  30. */
  31. static u8 lane_to_slot[] = {
  32. 0, 0, 0, 0, 0, 0, 0, 0
  33. };
  34. /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  35. * housed.
  36. */
  37. static int riser_phy_addr[] = {
  38. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
  39. CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
  40. CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
  41. CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
  42. };
  43. /* Slot2 does not have EMI connections */
  44. #define EMI_NONE 0xFFFFFFFF
  45. #define EMI1_RGMII0 0
  46. #define EMI1_RGMII1 1
  47. #define EMI1_SLOT1 2
  48. #define EMI1_SLOT3 3
  49. #define EMI1_SLOT4 4
  50. #define EMI1_SLOT5 5
  51. #define EMI1_SLOT6 6
  52. #define EMI1_SLOT7 7
  53. #define EMI2 8
  54. static int mdio_mux[NUM_FM_PORTS];
  55. static const char * const mdio_names[] = {
  56. "T1040_QDS_MDIO0",
  57. "T1040_QDS_MDIO1",
  58. "T1040_QDS_MDIO2",
  59. "T1040_QDS_MDIO3",
  60. "T1040_QDS_MDIO4",
  61. "T1040_QDS_MDIO5",
  62. "T1040_QDS_MDIO6",
  63. "T1040_QDS_MDIO7",
  64. };
  65. struct t1040_qds_mdio {
  66. u8 muxval;
  67. struct mii_dev *realbus;
  68. };
  69. static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
  70. {
  71. return mdio_names[muxval];
  72. }
  73. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  74. {
  75. struct mii_dev *bus;
  76. const char *name = t1040_qds_mdio_name_for_muxval(muxval);
  77. if (!name) {
  78. printf("No bus for muxval %x\n", muxval);
  79. return NULL;
  80. }
  81. bus = miiphy_get_dev_by_name(name);
  82. if (!bus) {
  83. printf("No bus by name %s\n", name);
  84. return NULL;
  85. }
  86. return bus;
  87. }
  88. static void t1040_qds_mux_mdio(u8 muxval)
  89. {
  90. u8 brdcfg4;
  91. if (muxval <= 7) {
  92. brdcfg4 = QIXIS_READ(brdcfg[4]);
  93. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  94. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  95. QIXIS_WRITE(brdcfg[4], brdcfg4);
  96. }
  97. }
  98. static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
  99. int regnum)
  100. {
  101. struct t1040_qds_mdio *priv = bus->priv;
  102. t1040_qds_mux_mdio(priv->muxval);
  103. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  104. }
  105. static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  106. int regnum, u16 value)
  107. {
  108. struct t1040_qds_mdio *priv = bus->priv;
  109. t1040_qds_mux_mdio(priv->muxval);
  110. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  111. }
  112. static int t1040_qds_mdio_reset(struct mii_dev *bus)
  113. {
  114. struct t1040_qds_mdio *priv = bus->priv;
  115. return priv->realbus->reset(priv->realbus);
  116. }
  117. static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
  118. {
  119. struct t1040_qds_mdio *pmdio;
  120. struct mii_dev *bus = mdio_alloc();
  121. if (!bus) {
  122. printf("Failed to allocate t1040_qds MDIO bus\n");
  123. return -1;
  124. }
  125. pmdio = malloc(sizeof(*pmdio));
  126. if (!pmdio) {
  127. printf("Failed to allocate t1040_qds private data\n");
  128. free(bus);
  129. return -1;
  130. }
  131. bus->read = t1040_qds_mdio_read;
  132. bus->write = t1040_qds_mdio_write;
  133. bus->reset = t1040_qds_mdio_reset;
  134. strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
  135. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  136. if (!pmdio->realbus) {
  137. printf("No bus with name %s\n", realbusname);
  138. free(bus);
  139. free(pmdio);
  140. return -1;
  141. }
  142. pmdio->muxval = muxval;
  143. bus->priv = pmdio;
  144. return mdio_register(bus);
  145. }
  146. /*
  147. * Initialize the lane_to_slot[] array.
  148. *
  149. * On the T1040QDS board the mapping is controlled by ?? register.
  150. */
  151. static void initialize_lane_to_slot(void)
  152. {
  153. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  154. int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
  155. FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
  156. >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  157. QIXIS_WRITE(cms[0], 0x07);
  158. switch (serdes1_prtcl) {
  159. case 0x60:
  160. case 0x66:
  161. case 0x67:
  162. case 0x69:
  163. lane_to_slot[1] = 7;
  164. lane_to_slot[2] = 6;
  165. lane_to_slot[3] = 5;
  166. break;
  167. case 0x86:
  168. lane_to_slot[1] = 7;
  169. lane_to_slot[2] = 7;
  170. lane_to_slot[3] = 7;
  171. break;
  172. case 0x87:
  173. lane_to_slot[1] = 7;
  174. lane_to_slot[2] = 7;
  175. lane_to_slot[3] = 7;
  176. lane_to_slot[7] = 7;
  177. break;
  178. case 0x89:
  179. lane_to_slot[1] = 7;
  180. lane_to_slot[2] = 7;
  181. lane_to_slot[3] = 7;
  182. lane_to_slot[6] = 7;
  183. lane_to_slot[7] = 7;
  184. break;
  185. case 0x8d:
  186. lane_to_slot[1] = 7;
  187. lane_to_slot[2] = 7;
  188. lane_to_slot[3] = 7;
  189. lane_to_slot[5] = 3;
  190. lane_to_slot[6] = 3;
  191. lane_to_slot[7] = 3;
  192. break;
  193. case 0x8F:
  194. case 0x85:
  195. lane_to_slot[1] = 7;
  196. lane_to_slot[2] = 6;
  197. lane_to_slot[3] = 5;
  198. lane_to_slot[6] = 3;
  199. lane_to_slot[7] = 3;
  200. break;
  201. case 0xA5:
  202. lane_to_slot[1] = 7;
  203. lane_to_slot[6] = 3;
  204. lane_to_slot[7] = 3;
  205. break;
  206. case 0xA7:
  207. lane_to_slot[1] = 7;
  208. lane_to_slot[2] = 6;
  209. lane_to_slot[3] = 5;
  210. lane_to_slot[7] = 7;
  211. break;
  212. case 0xAA:
  213. lane_to_slot[1] = 7;
  214. lane_to_slot[6] = 7;
  215. lane_to_slot[7] = 7;
  216. break;
  217. case 0x40:
  218. lane_to_slot[2] = 7;
  219. lane_to_slot[3] = 7;
  220. break;
  221. default:
  222. printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
  223. serdes1_prtcl);
  224. break;
  225. }
  226. }
  227. /*
  228. * Given the following ...
  229. *
  230. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  231. * compatible string and 'addr' physical address)
  232. *
  233. * 2) An Fman port
  234. *
  235. * ... update the phy-handle property of the Ethernet node to point to the
  236. * right PHY. This assumes that we already know the PHY for each port.
  237. *
  238. * The offset of the Fman Ethernet node is also passed in for convenience, but
  239. * it is not used, and we recalculate the offset anyway.
  240. *
  241. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  242. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  243. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  244. * and ports are the same thing.
  245. *
  246. */
  247. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  248. enum fm_port port, int offset)
  249. {
  250. phy_interface_t intf = fm_info_get_enet_if(port);
  251. char phy[16];
  252. /* The RGMII PHY is identified by the MAC connected to it */
  253. if (intf == PHY_INTERFACE_MODE_RGMII) {
  254. sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
  255. fdt_set_phy_handle(fdt, compat, addr, phy);
  256. }
  257. /* The SGMII PHY is identified by the MAC connected to it */
  258. if (intf == PHY_INTERFACE_MODE_SGMII) {
  259. int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
  260. + port);
  261. u8 slot;
  262. if (lane < 0)
  263. return;
  264. slot = lane_to_slot[lane];
  265. if (slot) {
  266. /* Slot housing a SGMII riser card */
  267. sprintf(phy, "phy_s%x_%02x", slot,
  268. (fm_info_get_phy_address(port - FM1_DTSEC1)-
  269. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
  270. fdt_set_phy_handle(fdt, compat, addr, phy);
  271. }
  272. }
  273. }
  274. void fdt_fixup_board_enet(void *fdt)
  275. {
  276. int i, lane, idx;
  277. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  278. idx = i - FM1_DTSEC1;
  279. switch (fm_info_get_enet_if(i)) {
  280. case PHY_INTERFACE_MODE_SGMII:
  281. lane = serdes_get_first_lane(FSL_SRDS_1,
  282. SGMII_FM1_DTSEC1 + idx);
  283. if (lane < 0)
  284. break;
  285. switch (mdio_mux[i]) {
  286. case EMI1_SLOT3:
  287. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  288. break;
  289. case EMI1_SLOT5:
  290. fdt_status_okay_by_alias(fdt, "emi1_slot5");
  291. break;
  292. case EMI1_SLOT6:
  293. fdt_status_okay_by_alias(fdt, "emi1_slot6");
  294. break;
  295. case EMI1_SLOT7:
  296. fdt_status_okay_by_alias(fdt, "emi1_slot7");
  297. break;
  298. }
  299. break;
  300. case PHY_INTERFACE_MODE_RGMII:
  301. if (i == FM1_DTSEC4)
  302. fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
  303. if (i == FM1_DTSEC5)
  304. fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
  305. break;
  306. default:
  307. break;
  308. }
  309. }
  310. }
  311. #endif /* #ifdef CONFIG_FMAN_ENET */
  312. static void set_brdcfg9_for_gtx_clk(void)
  313. {
  314. u8 brdcfg9;
  315. brdcfg9 = QIXIS_READ(brdcfg[9]);
  316. /* Initializing EPHY2 clock to RGMII mode */
  317. brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
  318. brdcfg9 |= (BRDCFG9_EPHY2_VAL);
  319. QIXIS_WRITE(brdcfg[9], brdcfg9);
  320. }
  321. void t1040_handle_phy_interface_sgmii(int i)
  322. {
  323. int lane, idx, slot;
  324. idx = i - FM1_DTSEC1;
  325. lane = serdes_get_first_lane(FSL_SRDS_1,
  326. SGMII_FM1_DTSEC1 + idx);
  327. if (lane < 0)
  328. return;
  329. slot = lane_to_slot[lane];
  330. switch (slot) {
  331. case 1:
  332. mdio_mux[i] = EMI1_SLOT1;
  333. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  334. break;
  335. case 3:
  336. if (FM1_DTSEC4 == i)
  337. fm_info_set_phy_address(i, riser_phy_addr[0]);
  338. if (FM1_DTSEC5 == i)
  339. fm_info_set_phy_address(i, riser_phy_addr[1]);
  340. mdio_mux[i] = EMI1_SLOT3;
  341. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  342. break;
  343. case 4:
  344. mdio_mux[i] = EMI1_SLOT4;
  345. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  346. break;
  347. case 5:
  348. /* Slot housing a SGMII riser card? */
  349. fm_info_set_phy_address(i, riser_phy_addr[0]);
  350. mdio_mux[i] = EMI1_SLOT5;
  351. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  352. break;
  353. case 6:
  354. /* Slot housing a SGMII riser card? */
  355. fm_info_set_phy_address(i, riser_phy_addr[0]);
  356. mdio_mux[i] = EMI1_SLOT6;
  357. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  358. break;
  359. case 7:
  360. if (FM1_DTSEC1 == i)
  361. fm_info_set_phy_address(i, riser_phy_addr[0]);
  362. if (FM1_DTSEC2 == i)
  363. fm_info_set_phy_address(i, riser_phy_addr[1]);
  364. if (FM1_DTSEC3 == i)
  365. fm_info_set_phy_address(i, riser_phy_addr[2]);
  366. if (FM1_DTSEC5 == i)
  367. fm_info_set_phy_address(i, riser_phy_addr[3]);
  368. mdio_mux[i] = EMI1_SLOT7;
  369. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  370. break;
  371. default:
  372. break;
  373. }
  374. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  375. }
  376. void t1040_handle_phy_interface_rgmii(int i)
  377. {
  378. fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
  379. CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
  380. CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  381. mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
  382. EMI1_RGMII0;
  383. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  384. }
  385. int board_eth_init(bd_t *bis)
  386. {
  387. #ifdef CONFIG_FMAN_ENET
  388. struct memac_mdio_info memac_mdio_info;
  389. unsigned int i;
  390. #ifdef CONFIG_VSC9953
  391. int lane;
  392. int phy_addr;
  393. phy_interface_t phy_int;
  394. struct mii_dev *bus;
  395. #endif
  396. printf("Initializing Fman\n");
  397. set_brdcfg9_for_gtx_clk();
  398. initialize_lane_to_slot();
  399. /* Initialize the mdio_mux array so we can recognize empty elements */
  400. for (i = 0; i < NUM_FM_PORTS; i++)
  401. mdio_mux[i] = EMI_NONE;
  402. memac_mdio_info.regs =
  403. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  404. memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  405. /* Register the real 1G MDIO bus */
  406. fm_memac_mdio_init(bis, &memac_mdio_info);
  407. /* Register the muxing front-ends to the MDIO buses */
  408. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
  409. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  410. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  411. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  412. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  413. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  414. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
  415. t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  416. /*
  417. * Program on board RGMII PHY addresses. If the SGMII Riser
  418. * card used, we'll override the PHY address later. For any DTSEC that
  419. * is RGMII, we'll also override its PHY address later. We assume that
  420. * DTSEC4 and DTSEC5 are used for RGMII.
  421. */
  422. fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  423. fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
  424. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  425. switch (fm_info_get_enet_if(i)) {
  426. case PHY_INTERFACE_MODE_QSGMII:
  427. fm_info_set_mdio(i, NULL);
  428. break;
  429. case PHY_INTERFACE_MODE_SGMII:
  430. t1040_handle_phy_interface_sgmii(i);
  431. break;
  432. case PHY_INTERFACE_MODE_RGMII:
  433. /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
  434. t1040_handle_phy_interface_rgmii(i);
  435. break;
  436. default:
  437. break;
  438. }
  439. }
  440. #ifdef CONFIG_VSC9953
  441. for (i = 0; i < VSC9953_MAX_PORTS; i++) {
  442. lane = -1;
  443. phy_addr = 0;
  444. phy_int = PHY_INTERFACE_MODE_NONE;
  445. switch (i) {
  446. case 0:
  447. case 1:
  448. case 2:
  449. case 3:
  450. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
  451. /* PHYs connected over QSGMII */
  452. if (lane >= 0) {
  453. phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
  454. i;
  455. phy_int = PHY_INTERFACE_MODE_QSGMII;
  456. break;
  457. }
  458. lane = serdes_get_first_lane(FSL_SRDS_1,
  459. SGMII_SW1_MAC1 + i);
  460. if (lane < 0)
  461. break;
  462. /* PHYs connected over QSGMII */
  463. if (i != 3 || lane_to_slot[lane] == 7)
  464. phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
  465. + i;
  466. else
  467. phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
  468. phy_int = PHY_INTERFACE_MODE_SGMII;
  469. break;
  470. case 4:
  471. case 5:
  472. case 6:
  473. case 7:
  474. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
  475. /* PHYs connected over QSGMII */
  476. if (lane >= 0) {
  477. phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
  478. i - 4;
  479. phy_int = PHY_INTERFACE_MODE_QSGMII;
  480. break;
  481. }
  482. lane = serdes_get_first_lane(FSL_SRDS_1,
  483. SGMII_SW1_MAC1 + i);
  484. /* PHYs connected over SGMII */
  485. if (lane >= 0) {
  486. phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
  487. + i - 3;
  488. phy_int = PHY_INTERFACE_MODE_SGMII;
  489. }
  490. break;
  491. case 8:
  492. if (serdes_get_first_lane(FSL_SRDS_1,
  493. SGMII_FM1_DTSEC1) < 0)
  494. /* FM1@DTSEC1 is connected to SW1@PORT8 */
  495. vsc9953_port_enable(i);
  496. break;
  497. case 9:
  498. if (serdes_get_first_lane(FSL_SRDS_1,
  499. SGMII_FM1_DTSEC2) < 0) {
  500. /* Enable L2 On MAC2 using SCFG */
  501. struct ccsr_scfg *scfg = (struct ccsr_scfg *)
  502. CONFIG_SYS_MPC85xx_SCFG;
  503. out_be32(&scfg->esgmiiselcr,
  504. in_be32(&scfg->esgmiiselcr) |
  505. (0x80000000));
  506. vsc9953_port_enable(i);
  507. }
  508. break;
  509. }
  510. if (lane >= 0) {
  511. bus = mii_dev_for_muxval(lane_to_slot[lane]);
  512. vsc9953_port_info_set_mdio(i, bus);
  513. vsc9953_port_enable(i);
  514. }
  515. vsc9953_port_info_set_phy_address(i, phy_addr);
  516. vsc9953_port_info_set_phy_int(i, phy_int);
  517. }
  518. #endif
  519. cpu_eth_init(bis);
  520. #endif
  521. return pci_eth_init(bis);
  522. }