diu.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <linux/ctype.h>
  9. #include <asm/io.h>
  10. #include <stdio_dev.h>
  11. #include <video_fb.h>
  12. #include <fsl_diu_fb.h>
  13. #include "../common/qixis.h"
  14. #include "../common/diu_ch7301.h"
  15. #include "t1040qds.h"
  16. #include "t1040qds_qixis.h"
  17. /*
  18. * DIU Area Descriptor
  19. *
  20. * Note that we need to byte-swap the value before it's written to the AD
  21. * register. So even though the registers don't look like they're in the same
  22. * bit positions as they are on the MPC8610, the same value is written to the
  23. * AD register on the MPC8610 and on the P1022.
  24. */
  25. #define AD_BYTE_F 0x10000000
  26. #define AD_ALPHA_C_SHIFT 25
  27. #define AD_BLUE_C_SHIFT 23
  28. #define AD_GREEN_C_SHIFT 21
  29. #define AD_RED_C_SHIFT 19
  30. #define AD_PIXEL_S_SHIFT 16
  31. #define AD_COMP_3_SHIFT 12
  32. #define AD_COMP_2_SHIFT 8
  33. #define AD_COMP_1_SHIFT 4
  34. #define AD_COMP_0_SHIFT 0
  35. void diu_set_pixel_clock(unsigned int pixclock)
  36. {
  37. unsigned long speed_ccb, temp;
  38. u32 pixval;
  39. int ret = 0;
  40. speed_ccb = get_bus_freq(0);
  41. temp = 1000000000 / pixclock;
  42. temp *= 1000;
  43. pixval = speed_ccb / temp;
  44. /* Program HDMI encoder */
  45. /* Switch channel to DIU */
  46. select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
  47. /* Set dispaly encoder */
  48. ret = diu_set_dvi_encoder(temp);
  49. if (ret) {
  50. puts("Failed to set DVI encoder\n");
  51. return;
  52. }
  53. /* Switch channel to default */
  54. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  55. /* Program pixel clock */
  56. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
  57. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  58. /* enable clock*/
  59. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
  60. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  61. }
  62. int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
  63. {
  64. u32 pixel_format;
  65. u8 sw;
  66. /*Route I2C4 to DIU system as HSYNC/VSYNC*/
  67. sw = QIXIS_READ(brdcfg[5]);
  68. QIXIS_WRITE(brdcfg[5],
  69. ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
  70. /*Configure Display ouput port as HDMI*/
  71. sw = QIXIS_READ(brdcfg[15]);
  72. QIXIS_WRITE(brdcfg[15],
  73. ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
  74. | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
  75. pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
  76. (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
  77. (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
  78. (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
  79. (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
  80. printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
  81. return fsl_diu_init(xres, yres, pixel_format, 0);
  82. }