ddr.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DDR_H__
  6. #define __DDR_H__
  7. struct board_specific_parameters {
  8. u32 n_ranks;
  9. u32 datarate_mhz_high;
  10. u32 rank_gb;
  11. u32 clk_adjust;
  12. u32 wrlvl_start;
  13. u32 wrlvl_ctl_2;
  14. u32 wrlvl_ctl_3;
  15. };
  16. /*
  17. * These tables contain all valid speeds we want to override with board
  18. * specific parameters. datarate_mhz_high values need to be in ascending order
  19. * for each n_ranks group.
  20. */
  21. static const struct board_specific_parameters udimm0[] = {
  22. /*
  23. * memory controller 0
  24. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
  25. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
  26. */
  27. #ifdef CONFIG_SYS_FSL_DDR4
  28. {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
  29. {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
  30. {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
  31. {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
  32. {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
  33. #elif defined(CONFIG_SYS_FSL_DDR3)
  34. {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
  35. {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
  36. {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
  37. {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
  38. {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
  39. {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
  40. #else
  41. #error DDR type not defined
  42. #endif
  43. {}
  44. };
  45. static const struct board_specific_parameters *udimms[] = {
  46. udimm0,
  47. };
  48. #endif