ddr.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <asm/mmu.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <fsl_ddr_dimm_params.h>
  11. #include <asm/fsl_law.h>
  12. #include <asm/mpc85xx_gpio.h>
  13. #include "ddr.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. void fsl_ddr_board_options(memctl_options_t *popts,
  16. dimm_params_t *pdimm,
  17. unsigned int ctrl_num)
  18. {
  19. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  20. ulong ddr_freq;
  21. if (ctrl_num > 2) {
  22. printf("Not supported controller number %d\n", ctrl_num);
  23. return;
  24. }
  25. if (!pdimm->n_ranks)
  26. return;
  27. pbsp = udimms[0];
  28. /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
  29. * freqency and n_banks specified in board_specific_parameters table.
  30. */
  31. ddr_freq = get_ddr_freq(0) / 1000000;
  32. while (pbsp->datarate_mhz_high) {
  33. if (pbsp->n_ranks == pdimm->n_ranks &&
  34. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  35. if (ddr_freq <= pbsp->datarate_mhz_high) {
  36. popts->clk_adjust = pbsp->clk_adjust;
  37. popts->wrlvl_start = pbsp->wrlvl_start;
  38. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  39. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  40. goto found;
  41. }
  42. pbsp_highest = pbsp;
  43. }
  44. pbsp++;
  45. }
  46. if (pbsp_highest) {
  47. printf("Error: board specific timing not found\n");
  48. printf("for data rate %lu MT/s\n", ddr_freq);
  49. printf("Trying to use the highest speed (%u) parameters\n",
  50. pbsp_highest->datarate_mhz_high);
  51. popts->clk_adjust = pbsp_highest->clk_adjust;
  52. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  53. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  54. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  55. } else {
  56. panic("DIMM is not supported by this board");
  57. }
  58. found:
  59. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  60. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  61. "wrlvl_ctrl_3 0x%x\n",
  62. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  63. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  64. pbsp->wrlvl_ctl_3);
  65. /*
  66. * Factors to consider for half-strength driver enable:
  67. * - number of DIMMs installed
  68. */
  69. popts->half_strength_driver_enable = 1;
  70. /*
  71. * Write leveling override
  72. */
  73. popts->wrlvl_override = 1;
  74. popts->wrlvl_sample = 0xf;
  75. /*
  76. * rtt and rtt_wr override
  77. */
  78. popts->rtt_override = 0;
  79. /* Enable ZQ calibration */
  80. popts->zq_en = 1;
  81. /* DHC_EN =1, ODT = 75 Ohm */
  82. #ifdef CONFIG_SYS_FSL_DDR4
  83. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  84. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  85. DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
  86. /* optimize cpo for erratum A-009942 */
  87. popts->cpo_sample = 0x69;
  88. #else
  89. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  90. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  91. #endif
  92. }
  93. #if defined(CONFIG_DEEP_SLEEP)
  94. void board_mem_sleep_setup(void)
  95. {
  96. void __iomem *qixis_base = (void *)QIXIS_BASE;
  97. /* does not provide HW signals for power management */
  98. clrbits_8(qixis_base + 0x21, 0x2);
  99. /* Disable MCKE isolation */
  100. gpio_set_value(2, 0);
  101. udelay(1);
  102. }
  103. #endif
  104. int dram_init(void)
  105. {
  106. phys_size_t dram_size;
  107. puts("Initializing....using SPD\n");
  108. dram_size = fsl_ddr_sdram();
  109. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  110. dram_size *= 0x100000;
  111. puts(" DDR: ");
  112. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  113. fsl_dp_resume();
  114. #endif
  115. gd->ram_size = dram_size;
  116. return 0;
  117. }