eth_t102xrdb.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. *
  5. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <netdev.h>
  10. #include <asm/mmu.h>
  11. #include <asm/processor.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/fsl_law.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/fsl_portals.h>
  16. #include <asm/fsl_liodn.h>
  17. #include <malloc.h>
  18. #include <fm_eth.h>
  19. #include <fsl_mdio.h>
  20. #include <miiphy.h>
  21. #include <phy.h>
  22. #include <fsl_dtsec.h>
  23. #include <asm/fsl_serdes.h>
  24. #include "../common/fman.h"
  25. int board_eth_init(bd_t *bis)
  26. {
  27. #if defined(CONFIG_FMAN_ENET)
  28. int i, interface;
  29. struct memac_mdio_info dtsec_mdio_info;
  30. struct memac_mdio_info tgec_mdio_info;
  31. struct mii_dev *dev;
  32. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  33. u32 srds_s1;
  34. srds_s1 = in_be32(&gur->rcwsr[4]) &
  35. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  36. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  37. dtsec_mdio_info.regs =
  38. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  39. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  40. /* Register the 1G MDIO bus */
  41. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  42. tgec_mdio_info.regs =
  43. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  44. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  45. /* Register the 10G MDIO bus */
  46. fm_memac_mdio_init(bis, &tgec_mdio_info);
  47. /* Set the on-board RGMII PHY address */
  48. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
  49. switch (srds_s1) {
  50. #ifdef CONFIG_TARGET_T1024RDB
  51. case 0x95:
  52. /* set the on-board RGMII2 PHY */
  53. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
  54. /* set 10G XFI with Aquantia AQR105 PHY */
  55. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  56. break;
  57. #endif
  58. case 0x6a:
  59. case 0x6b:
  60. case 0x77:
  61. case 0x135:
  62. /* set the on-board 2.5G SGMII AQR105 PHY */
  63. fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
  64. #ifdef CONFIG_TARGET_T1023RDB
  65. /* set the on-board 1G SGMII RTL8211F PHY */
  66. fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
  67. #endif
  68. break;
  69. default:
  70. printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
  71. srds_s1);
  72. break;
  73. }
  74. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  75. interface = fm_info_get_enet_if(i);
  76. switch (interface) {
  77. case PHY_INTERFACE_MODE_RGMII:
  78. dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  79. fm_info_set_mdio(i, dev);
  80. break;
  81. case PHY_INTERFACE_MODE_SGMII:
  82. #if defined(CONFIG_TARGET_T1023RDB)
  83. dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  84. #elif defined(CONFIG_TARGET_T1024RDB)
  85. dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  86. #endif
  87. fm_info_set_mdio(i, dev);
  88. break;
  89. case PHY_INTERFACE_MODE_SGMII_2500:
  90. dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  91. fm_info_set_mdio(i, dev);
  92. break;
  93. default:
  94. break;
  95. }
  96. }
  97. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  98. switch (fm_info_get_enet_if(i)) {
  99. case PHY_INTERFACE_MODE_XGMII:
  100. dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  101. fm_info_set_mdio(i, dev);
  102. break;
  103. default:
  104. break;
  105. }
  106. }
  107. cpu_eth_init(bis);
  108. #endif /* CONFIG_FMAN_ENET */
  109. return pci_eth_init(bis);
  110. }
  111. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  112. enum fm_port port, int offset)
  113. {
  114. #if defined(CONFIG_TARGET_T1024RDB)
  115. if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
  116. (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
  117. (port == FM1_DTSEC3)) {
  118. fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
  119. fdt_setprop_string(fdt, offset, "phy-connection-type",
  120. "sgmii-2500");
  121. fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
  122. }
  123. #endif
  124. }
  125. void fdt_fixup_board_enet(void *fdt)
  126. {
  127. }