eth.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. * Author: Mingkai Hu <Mingkai.hu@freescale.com>
  5. */
  6. /*
  7. * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
  8. * are provided by the three on-board PHY or by the standard Freescale
  9. * four-port SGMII riser card. We need to change the phy-handle in the
  10. * kernel dts file to point to the correct PHY according to serdes mux
  11. * and serdes protocol selection.
  12. */
  13. #include <common.h>
  14. #include <netdev.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <fm_eth.h>
  17. #include <fsl_mdio.h>
  18. #include <malloc.h>
  19. #include <fsl_dtsec.h>
  20. #include "cpld.h"
  21. #include "../common/fman.h"
  22. #ifdef CONFIG_FMAN_ENET
  23. /*
  24. * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
  25. * that the mapping must be determined dynamically, or that the lane maps to
  26. * something other than a board slot
  27. */
  28. static u8 lane_to_slot[] = {
  29. 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
  30. };
  31. static int riser_phy_addr[] = {
  32. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
  33. CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
  34. CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
  35. CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
  36. };
  37. /*
  38. * Initialize the lane_to_slot[] array.
  39. *
  40. * On the P2040RDB board the mapping is controlled by CPLD register.
  41. */
  42. static void initialize_lane_to_slot(void)
  43. {
  44. u8 mux = CPLD_READ(serdes_mux);
  45. lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
  46. lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
  47. lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
  48. lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
  49. }
  50. /*
  51. * Given the following ...
  52. *
  53. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  54. * compatible string and 'addr' physical address)
  55. *
  56. * 2) An Fman port
  57. *
  58. * ... update the phy-handle property of the Ethernet node to point to the
  59. * right PHY. This assumes that we already know the PHY for each port.
  60. *
  61. * The offset of the Fman Ethernet node is also passed in for convenience, but
  62. * it is not used, and we recalculate the offset anyway.
  63. *
  64. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  65. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  66. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  67. * and ports are the same thing.
  68. *
  69. */
  70. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  71. enum fm_port port, int offset)
  72. {
  73. phy_interface_t intf = fm_info_get_enet_if(port);
  74. char phy[16];
  75. /* The RGMII PHY is identified by the MAC connected to it */
  76. if (intf == PHY_INTERFACE_MODE_RGMII) {
  77. sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
  78. fdt_set_phy_handle(fdt, compat, addr, phy);
  79. }
  80. /* The SGMII PHY is identified by the MAC connected to it */
  81. if (intf == PHY_INTERFACE_MODE_SGMII) {
  82. int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
  83. u8 slot;
  84. if (lane < 0)
  85. return;
  86. slot = lane_to_slot[lane];
  87. if (slot) {
  88. sprintf(phy, "phy_sgmii_%x",
  89. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
  90. + (port - FM1_DTSEC1));
  91. fdt_set_phy_handle(fdt, compat, addr, phy);
  92. } else {
  93. sprintf(phy, "phy_sgmii_%x",
  94. CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
  95. + (port - FM1_DTSEC1));
  96. fdt_set_phy_handle(fdt, compat, addr, phy);
  97. }
  98. }
  99. if (intf == PHY_INTERFACE_MODE_XGMII) {
  100. /* XAUI */
  101. int lane = serdes_get_first_lane(XAUI_FM1);
  102. if (lane >= 0) {
  103. /* The XAUI PHY is identified by the slot */
  104. sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
  105. fdt_set_phy_handle(fdt, compat, addr, phy);
  106. }
  107. }
  108. }
  109. #endif /* #ifdef CONFIG_FMAN_ENET */
  110. int board_eth_init(bd_t *bis)
  111. {
  112. #ifdef CONFIG_FMAN_ENET
  113. struct fsl_pq_mdio_info dtsec_mdio_info;
  114. struct tgec_mdio_info tgec_mdio_info;
  115. unsigned int i, slot;
  116. int lane;
  117. printf("Initializing Fman\n");
  118. initialize_lane_to_slot();
  119. dtsec_mdio_info.regs =
  120. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  121. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  122. /* Register the real 1G MDIO bus */
  123. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  124. tgec_mdio_info.regs =
  125. (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  126. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  127. /* Register the real 10G MDIO bus */
  128. fm_tgec_mdio_init(bis, &tgec_mdio_info);
  129. /*
  130. * Program the three on-board SGMII PHY addresses. If the SGMII Riser
  131. * card used, we'll override the PHY address later. For any DTSEC that
  132. * is RGMII, we'll also override its PHY address later. We assume that
  133. * DTSEC4 and DTSEC5 are used for RGMII.
  134. */
  135. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  136. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  137. fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
  138. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  139. int idx = i - FM1_DTSEC1;
  140. switch (fm_info_get_enet_if(i)) {
  141. case PHY_INTERFACE_MODE_SGMII:
  142. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  143. if (lane < 0)
  144. break;
  145. slot = lane_to_slot[lane];
  146. if (slot)
  147. fm_info_set_phy_address(i, riser_phy_addr[i]);
  148. break;
  149. case PHY_INTERFACE_MODE_RGMII:
  150. /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
  151. fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
  152. CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
  153. CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  154. break;
  155. default:
  156. printf("Fman1: DTSEC%u set to unknown interface %i\n",
  157. idx + 1, fm_info_get_enet_if(i));
  158. break;
  159. }
  160. fm_info_set_mdio(i,
  161. miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  162. }
  163. lane = serdes_get_first_lane(XAUI_FM1);
  164. if (lane >= 0) {
  165. slot = lane_to_slot[lane];
  166. if (slot)
  167. fm_info_set_phy_address(FM1_10GEC1,
  168. CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  169. }
  170. fm_info_set_mdio(FM1_10GEC1,
  171. miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
  172. cpu_eth_init(bis);
  173. #endif
  174. return pci_eth_init(bis);
  175. }