ddr.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <asm/mmu.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <fsl_ddr_dimm_params.h>
  11. #include <asm/fsl_law.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. struct board_specific_parameters {
  14. u32 n_ranks;
  15. u32 datarate_mhz_high;
  16. u32 clk_adjust;
  17. u32 wrlvl_start;
  18. u32 cpo;
  19. u32 write_data_delay;
  20. u32 force_2t;
  21. };
  22. /*
  23. * This table contains all valid speeds we want to override with board
  24. * specific parameters. datarate_mhz_high values need to be in ascending order
  25. * for each n_ranks group.
  26. *
  27. * ranges for parameters:
  28. * wr_data_delay = 0-6
  29. * clk adjust = 0-8
  30. * cpo 2-0x1E (30)
  31. */
  32. static const struct board_specific_parameters dimm0[] = {
  33. /*
  34. * memory controller 0
  35. * num| hi| clk| wrlvl | cpo |wrdata|2T
  36. * ranks| mhz|adjst| start | delay|
  37. */
  38. {2, 750, 3, 5, 0xff, 2, 0},
  39. {2, 1250, 4, 6, 0xff, 2, 0},
  40. {2, 1350, 5, 7, 0xff, 2, 0},
  41. {2, 1666, 5, 8, 0xff, 2, 0},
  42. {}
  43. };
  44. void fsl_ddr_board_options(memctl_options_t *popts,
  45. dimm_params_t *pdimm,
  46. unsigned int ctrl_num)
  47. {
  48. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  49. ulong ddr_freq;
  50. if (ctrl_num) {
  51. printf("Wrong parameter for controller number %d", ctrl_num);
  52. return;
  53. }
  54. if (!pdimm->n_ranks)
  55. return;
  56. pbsp = dimm0;
  57. /*
  58. * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  59. * freqency and n_banks specified in board_specific_parameters table.
  60. */
  61. ddr_freq = get_ddr_freq(0) / 1000000;
  62. while (pbsp->datarate_mhz_high) {
  63. if (pbsp->n_ranks == pdimm->n_ranks) {
  64. if (ddr_freq <= pbsp->datarate_mhz_high) {
  65. popts->cpo_override = pbsp->cpo;
  66. popts->write_data_delay =
  67. pbsp->write_data_delay;
  68. popts->clk_adjust = pbsp->clk_adjust;
  69. popts->wrlvl_start = pbsp->wrlvl_start;
  70. popts->twot_en = pbsp->force_2t;
  71. goto found;
  72. }
  73. pbsp_highest = pbsp;
  74. }
  75. pbsp++;
  76. }
  77. if (pbsp_highest) {
  78. printf("Error: board specific timing not found "
  79. "for data rate %lu MT/s!\n"
  80. "Trying to use the highest speed (%u) parameters\n",
  81. ddr_freq, pbsp_highest->datarate_mhz_high);
  82. popts->cpo_override = pbsp_highest->cpo;
  83. popts->write_data_delay = pbsp_highest->write_data_delay;
  84. popts->clk_adjust = pbsp_highest->clk_adjust;
  85. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  86. popts->twot_en = pbsp_highest->force_2t;
  87. } else {
  88. panic("DIMM is not supported by this board");
  89. }
  90. found:
  91. /*
  92. * Factors to consider for half-strength driver enable:
  93. * - number of DIMMs installed
  94. */
  95. popts->half_strength_driver_enable = 0;
  96. /* Write leveling override */
  97. popts->wrlvl_override = 1;
  98. popts->wrlvl_sample = 0xf;
  99. /* Rtt and Rtt_WR override */
  100. popts->rtt_override = 0;
  101. /* Enable ZQ calibration */
  102. popts->zq_en = 1;
  103. /* DHC_EN =1, ODT = 60 Ohm */
  104. popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
  105. }
  106. int dram_init(void)
  107. {
  108. phys_size_t dram_size = 0;
  109. puts("Initializing....");
  110. if (fsl_use_spd()) {
  111. puts("using SPD\n");
  112. dram_size = fsl_ddr_sdram();
  113. } else {
  114. puts("no SPD and fixed parameters\n");
  115. return -ENXIO;
  116. }
  117. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  118. dram_size *= 0x100000;
  119. debug(" DDR: ");
  120. gd->ram_size = dram_size;
  121. return 0;
  122. }