tlb.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. struct fsl_e_tlb_entry tlb_table[] = {
  8. /* TLB 0 - for temp stack in cache */
  9. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  10. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  11. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  12. 0, 0, BOOKE_PAGESZ_4K, 0),
  13. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
  14. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  15. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16. 0, 0, BOOKE_PAGESZ_4K, 0),
  17. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
  18. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
  22. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  23. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  24. 0, 0, BOOKE_PAGESZ_4K, 0),
  25. /* TLB 1 */
  26. /* *I*** - Covers boot page */
  27. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  28. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  29. 0, 0, BOOKE_PAGESZ_4K, 1),
  30. /* *I*G* - CCSRBAR */
  31. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  32. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  33. 0, 1, BOOKE_PAGESZ_1M, 1),
  34. #ifndef CONFIG_SPL_BUILD
  35. /* W**G* - Flash, localbus */
  36. /* This will be changed to *I*G* after relocation to RAM. */
  37. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  38. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  39. 0, 2, BOOKE_PAGESZ_64M, 1),
  40. /* W**G* - Flash, localbus */
  41. /* This will be changed to *I*G* after relocation to RAM. */
  42. SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
  43. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  44. 0, 5, BOOKE_PAGESZ_1M, 1),
  45. #ifdef CONFIG_PCI
  46. /* *I*G* - PCI memory 1.5G */
  47. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  48. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49. 0, 3, BOOKE_PAGESZ_1G, 1),
  50. /* *I*G* - PCI I/O effective: 192K */
  51. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  52. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53. 0, 4, BOOKE_PAGESZ_256K, 1),
  54. #endif
  55. #endif
  56. #ifdef CONFIG_SYS_RAMBOOT
  57. /* *I*G - eSDHC boot */
  58. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  59. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  60. 0, 8, BOOKE_PAGESZ_1G, 1),
  61. #endif
  62. };
  63. int num_tlb_entries = ARRAY_SIZE(tlb_table);