p1_twr.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <hwconfig.h>
  9. #include <init.h>
  10. #include <pci.h>
  11. #include <i2c.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_pci.h>
  17. #include <fsl_ddr_sdram.h>
  18. #include <asm/io.h>
  19. #include <asm/fsl_law.h>
  20. #include <asm/fsl_lbc.h>
  21. #include <asm/mp.h>
  22. #include <miiphy.h>
  23. #include <linux/libfdt.h>
  24. #include <fdt_support.h>
  25. #include <fsl_mdio.h>
  26. #include <tsec.h>
  27. #include <ioports.h>
  28. #include <asm/fsl_serdes.h>
  29. #include <netdev.h>
  30. #define SYSCLK_64 64000000
  31. #define SYSCLK_66 66666666
  32. unsigned long get_board_sys_clk(ulong dummy)
  33. {
  34. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35. par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
  36. unsigned int cpdat_val = 0;
  37. /* Set-up up pin muxing based on board switch settings */
  38. cpdat_val = par_io[1].cpdat;
  39. /* Check switch setting for SYSCLK select (PB3) */
  40. if (cpdat_val & 0x10000000)
  41. return SYSCLK_64;
  42. else
  43. return SYSCLK_66;
  44. return 0;
  45. }
  46. #ifdef CONFIG_QE
  47. #define PCA_IOPORT_I2C_ADDR 0x23
  48. #define PCA_IOPORT_OUTPUT_CMD 0x2
  49. #define PCA_IOPORT_CFG_CMD 0x6
  50. const qe_iop_conf_t qe_iop_conf_tab[] = {
  51. #ifdef CONFIG_TWR_P1025
  52. /* GPIO */
  53. {1, 0, 1, 0, 0},
  54. {1, 18, 1, 0, 0},
  55. /* GPIO for switch options */
  56. {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
  57. {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
  58. {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
  59. {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
  60. /* QE_MUX_MDC */
  61. {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
  62. /* QE_MUX_MDIO */
  63. {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
  64. /* UCC_1_MII */
  65. {0, 23, 2, 0, 2}, /* CLK12 */
  66. {0, 24, 2, 0, 1}, /* CLK9 */
  67. {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
  68. {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
  69. {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
  70. {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
  71. {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
  72. {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
  73. {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
  74. {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
  75. {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  76. {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
  77. {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
  78. {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
  79. {0, 17, 2, 0, 2}, /* ENET1_CRS */
  80. {0, 16, 2, 0, 2}, /* ENET1_COL */
  81. /* UCC_5_RMII */
  82. {1, 11, 2, 0, 1}, /* CLK13 */
  83. {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
  84. {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
  85. {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
  86. {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
  87. {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
  88. {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
  89. {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
  90. /* TDMA - clock option is configured in OS based on board setting */
  91. {1, 23, 2, 0, 2}, /* TDMA_TXD */
  92. {1, 25, 2, 0, 2}, /* TDMA_RXD */
  93. {1, 26, 1, 0, 2}, /* TDMA_SYNC */
  94. #endif
  95. {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
  96. };
  97. #endif
  98. int board_early_init_f(void)
  99. {
  100. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  101. setbits_be32(&gur->pmuxcr,
  102. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  103. /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
  104. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  105. return 0;
  106. }
  107. int checkboard(void)
  108. {
  109. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  110. u8 boot_status;
  111. printf("Board: %s\n", CONFIG_BOARDNAME);
  112. boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
  113. puts("rom_loc: ");
  114. if (boot_status == PORBMSR_ROMLOC_NOR)
  115. puts("nor flash");
  116. else if (boot_status == PORBMSR_ROMLOC_SDHC)
  117. puts("sd");
  118. else
  119. puts("unknown");
  120. puts("\n");
  121. return 0;
  122. }
  123. #ifdef CONFIG_PCI
  124. void pci_init_board(void)
  125. {
  126. fsl_pcie_init_board(0);
  127. }
  128. #endif
  129. int board_early_init_r(void)
  130. {
  131. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  132. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  133. /*
  134. * Remap Boot flash region to caching-inhibited
  135. * so that flash can be erased properly.
  136. */
  137. /* Flush d-cache and invalidate i-cache of any FLASH data */
  138. flush_dcache();
  139. invalidate_icache();
  140. if (flash_esel == -1) {
  141. /* very unlikely unless something is messed up */
  142. puts("Error: Could not find TLB for FLASH BASE\n");
  143. flash_esel = 2; /* give our best effort to continue */
  144. } else {
  145. /* invalidate existing TLB entry for flash */
  146. disable_tlb(flash_esel);
  147. }
  148. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  149. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  150. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  151. return 0;
  152. }
  153. int board_eth_init(bd_t *bis)
  154. {
  155. struct fsl_pq_mdio_info mdio_info;
  156. struct tsec_info_struct tsec_info[4];
  157. ccsr_gur_t *gur __attribute__((unused)) =
  158. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  159. int num = 0;
  160. #ifdef CONFIG_TSEC1
  161. SET_STD_TSEC_INFO(tsec_info[num], 1);
  162. num++;
  163. #endif
  164. #ifdef CONFIG_TSEC2
  165. SET_STD_TSEC_INFO(tsec_info[num], 2);
  166. if (is_serdes_configured(SGMII_TSEC2)) {
  167. printf("eTSEC2 is in sgmii mode.\n");
  168. tsec_info[num].flags |= TSEC_SGMII;
  169. }
  170. num++;
  171. #endif
  172. #ifdef CONFIG_TSEC3
  173. SET_STD_TSEC_INFO(tsec_info[num], 3);
  174. num++;
  175. #endif
  176. if (!num) {
  177. printf("No TSECs initialized\n");
  178. return 0;
  179. }
  180. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  181. mdio_info.name = DEFAULT_MII_NAME;
  182. fsl_pq_mdio_init(bis, &mdio_info);
  183. tsec_eth_init(bis, tsec_info, num);
  184. #if defined(CONFIG_UEC_ETH)
  185. /* QE0 and QE3 need to be exposed for UCC1
  186. * and UCC5 Eth mode (in PMUXCR register).
  187. * Currently QE/LBC muxed pins assumed to be
  188. * LBC for U-Boot and PMUXCR updated by OS if required */
  189. uec_standard_init(bis);
  190. #endif
  191. return pci_eth_init(bis);
  192. }
  193. #if defined(CONFIG_QE)
  194. static void fdt_board_fixup_qe_pins(void *blob)
  195. {
  196. int node;
  197. if (!hwconfig("qe")) {
  198. /* For QE and eLBC pins multiplexing,
  199. * When don't use QE function, remove
  200. * qe node from dt blob.
  201. */
  202. node = fdt_path_offset(blob, "/qe");
  203. if (node >= 0)
  204. fdt_del_node(blob, node);
  205. } else {
  206. /* For TWR Peripheral Modules - TWR-SER2
  207. * board only can support Signal Port MII,
  208. * so delete one UEC node when use MII port.
  209. */
  210. if (hwconfig("mii"))
  211. node = fdt_path_offset(blob, "/qe/ucc@2400");
  212. else
  213. node = fdt_path_offset(blob, "/qe/ucc@2000");
  214. if (node >= 0)
  215. fdt_del_node(blob, node);
  216. }
  217. return;
  218. }
  219. #endif
  220. #ifdef CONFIG_OF_BOARD_SETUP
  221. int ft_board_setup(void *blob, bd_t *bd)
  222. {
  223. phys_addr_t base;
  224. phys_size_t size;
  225. ft_cpu_setup(blob, bd);
  226. base = env_get_bootm_low();
  227. size = env_get_bootm_size();
  228. fdt_fixup_memory(blob, (u64)base, (u64)size);
  229. FT_FSL_PCI_SETUP;
  230. #ifdef CONFIG_QE
  231. do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
  232. sizeof("okay"), 0);
  233. #endif
  234. #if defined(CONFIG_TWR_P1025)
  235. fdt_board_fixup_qe_pins(blob);
  236. #endif
  237. fsl_fdt_fixup_dr_usb(blob, bd);
  238. return 0;
  239. }
  240. #endif