tlb.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010 Freescale Semiconductor, Inc.
  4. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  5. * Timur Tabi <timur@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <asm/mmu.h>
  9. struct fsl_e_tlb_entry tlb_table[] = {
  10. /* TLB 0 - for temp stack in cache */
  11. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  12. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  13. 0, 0, BOOKE_PAGESZ_4K, 0),
  14. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  15. CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  19. CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  20. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  21. 0, 0, BOOKE_PAGESZ_4K, 0),
  22. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  23. CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25. 0, 0, BOOKE_PAGESZ_4K, 0),
  26. /* TLB 1 */
  27. /* *I*** - Covers boot page */
  28. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  29. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  30. 0, 0, BOOKE_PAGESZ_4K, 1),
  31. /* *I*G* - CCSRBAR */
  32. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  33. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  34. 0, 1, BOOKE_PAGESZ_1M, 1),
  35. #ifndef CONFIG_SPL_BUILD
  36. /* W**G* - Flash/promjet, localbus */
  37. /* This will be changed to *I*G* after relocation to RAM. */
  38. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  39. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  40. 0, 2, BOOKE_PAGESZ_256M, 1),
  41. /* *I*G* - PCI */
  42. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  43. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  44. 0, 3, BOOKE_PAGESZ_1G, 1),
  45. /* *I*G* - PCI */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
  47. CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
  48. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49. 0, 4, BOOKE_PAGESZ_256M, 1),
  50. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
  51. CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
  52. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53. 0, 5, BOOKE_PAGESZ_256M, 1),
  54. /* *I*G* - PCI I/O */
  55. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
  56. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57. 0, 6, BOOKE_PAGESZ_256K, 1),
  58. #endif
  59. SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
  60. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61. 0, 7, BOOKE_PAGESZ_4K, 1),
  62. #if defined(CONFIG_SYS_RAMBOOT) || \
  63. (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
  64. /* **** - eSDHC/eSPI/NAND boot */
  65. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  66. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  67. 0, 8, BOOKE_PAGESZ_1G, 1),
  68. /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
  69. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  70. CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
  71. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  72. 0, 9, BOOKE_PAGESZ_1G, 1),
  73. #endif
  74. #ifdef CONFIG_SYS_NAND_BASE
  75. /* *I*G - NAND */
  76. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  77. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  78. 0, 10, BOOKE_PAGESZ_16K, 1),
  79. #endif
  80. #ifdef CONFIG_SYS_INIT_L2_ADDR
  81. /* *I*G - L2SRAM */
  82. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  83. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
  84. 0, 11, BOOKE_PAGESZ_256K, 1)
  85. #endif
  86. };
  87. int num_tlb_entries = ARRAY_SIZE(tlb_table);