spl_minimal.c 1.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <ns16550.h>
  7. #include <asm/io.h>
  8. #include <nand.h>
  9. #include <asm/fsl_law.h>
  10. #include <fsl_ddr_sdram.h>
  11. const static u32 sysclk_tbl[] = {
  12. 66666000, 7499900, 83332500, 8999900,
  13. 99999000, 11111000, 12499800, 13333200
  14. };
  15. void board_init_f(ulong bootflag)
  16. {
  17. int px_spd;
  18. u32 plat_ratio, sys_clk, bus_clk;
  19. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  20. #if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
  21. set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  22. set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
  23. #endif
  24. /* for FPGA */
  25. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  26. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  27. /* initialize selected port with appropriate baud rate */
  28. px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
  29. sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
  30. plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  31. bus_clk = sys_clk * plat_ratio / 2;
  32. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  33. bus_clk / 16 / CONFIG_BAUDRATE);
  34. puts("\nNAND boot... ");
  35. /* copy code to RAM and jump to it - this should not return */
  36. /* NOTE - code has to be copied out of NAND buffer before
  37. * other blocks can be read.
  38. */
  39. relocate_code(CONFIG_SPL_RELOC_STACK, 0,
  40. CONFIG_SPL_RELOC_TEXT_BASE);
  41. }
  42. void board_init_r(gd_t *gd, ulong dest_addr)
  43. {
  44. puts("\nSecond program loader running in sram...");
  45. nand_boot();
  46. }
  47. void putc(char c)
  48. {
  49. if (c == '\n')
  50. NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
  51. NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
  52. }
  53. void puts(const char *str)
  54. {
  55. while (*str)
  56. putc(*str++);
  57. }