ddr.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010 Freescale Semiconductor, Inc.
  4. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  5. * Timur Tabi <timur@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <fsl_ddr_dimm_params.h>
  10. struct board_specific_parameters {
  11. u32 n_ranks;
  12. u32 datarate_mhz_high;
  13. u32 clk_adjust; /* Range: 0-8 */
  14. u32 cpo; /* Range: 2-31 */
  15. u32 write_data_delay; /* Range: 0-6 */
  16. u32 force_2t;
  17. };
  18. /*
  19. * This table contains all valid speeds we want to override with board
  20. * specific parameters. datarate_mhz_high values need to be in ascending order
  21. * for each n_ranks group.
  22. */
  23. static const struct board_specific_parameters dimm0[] = {
  24. /*
  25. * memory controller 0
  26. * num| hi| clk| cpo|wrdata|2T
  27. * ranks| mhz|adjst| | delay|
  28. */
  29. {1, 549, 5, 31, 3, 0},
  30. {1, 850, 5, 31, 5, 0},
  31. {2, 549, 5, 31, 3, 0},
  32. {2, 850, 5, 31, 5, 0},
  33. {}
  34. };
  35. void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
  36. unsigned int ctrl_num)
  37. {
  38. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  39. unsigned long ddr_freq;
  40. unsigned int i;
  41. if (ctrl_num) {
  42. printf("Wrong parameter for controller number %d", ctrl_num);
  43. return;
  44. }
  45. if (!pdimm->n_ranks)
  46. return;
  47. /* set odt_rd_cfg and odt_wr_cfg. */
  48. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  49. popts->cs_local_opts[i].odt_rd_cfg = 0;
  50. popts->cs_local_opts[i].odt_wr_cfg = 1;
  51. }
  52. pbsp = dimm0;
  53. /*
  54. * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  55. * freqency and n_banks specified in board_specific_parameters table.
  56. */
  57. ddr_freq = get_ddr_freq(0) / 1000000;
  58. while (pbsp->datarate_mhz_high) {
  59. if (pbsp->n_ranks == pdimm->n_ranks) {
  60. if (ddr_freq <= pbsp->datarate_mhz_high) {
  61. popts->clk_adjust = pbsp->clk_adjust;
  62. popts->cpo_override = pbsp->cpo;
  63. popts->write_data_delay =
  64. pbsp->write_data_delay;
  65. popts->twot_en = pbsp->force_2t;
  66. goto found;
  67. }
  68. pbsp_highest = pbsp;
  69. }
  70. pbsp++;
  71. }
  72. if (pbsp_highest) {
  73. printf("Error: board specific timing not found "
  74. "for data rate %lu MT/s!\n"
  75. "Trying to use the highest speed (%u) parameters\n",
  76. ddr_freq, pbsp_highest->datarate_mhz_high);
  77. popts->clk_adjust = pbsp->clk_adjust;
  78. popts->cpo_override = pbsp->cpo;
  79. popts->write_data_delay = pbsp->write_data_delay;
  80. popts->twot_en = pbsp->force_2t;
  81. } else {
  82. panic("DIMM is not supported by this board");
  83. }
  84. found:
  85. popts->half_strength_driver_enable = 1;
  86. /* Per AN4039, enable ZQ calibration. */
  87. popts->zq_en = 1;
  88. /*
  89. * For wake-up on ARP, we need auto self refresh enabled
  90. */
  91. popts->auto_self_refresh_en = 1;
  92. popts->sr_it = 0xb;
  93. }