mpc8610hpcd.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <init.h>
  8. #include <pci.h>
  9. #include <asm/processor.h>
  10. #include <asm/immap_86xx.h>
  11. #include <asm/fsl_pci.h>
  12. #include <fsl_ddr_sdram.h>
  13. #include <asm/fsl_serdes.h>
  14. #include <i2c.h>
  15. #include <asm/io.h>
  16. #include <linux/libfdt.h>
  17. #include <fdt_support.h>
  18. #include <spd_sdram.h>
  19. #include <netdev.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. void sdram_init(void);
  22. phys_size_t fixed_sdram(void);
  23. int mpc8610hpcd_diu_init(void);
  24. /* called before any console output */
  25. int board_early_init_f(void)
  26. {
  27. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  28. volatile ccsr_gur_t *gur = &immap->im_gur;
  29. gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
  30. return 0;
  31. }
  32. int misc_init_r(void)
  33. {
  34. u8 tmp_val, version;
  35. u8 *pixis_base = (u8 *)PIXIS_BASE;
  36. /*Do not use 8259PIC*/
  37. tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  38. out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
  39. /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
  40. version = in_8(pixis_base + PIXIS_PVER);
  41. if(version >= 0x07) {
  42. tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  43. out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
  44. }
  45. /* Using this for DIU init before the driver in linux takes over
  46. * Enable the TFP410 Encoder (I2C address 0x38)
  47. */
  48. tmp_val = 0xBF;
  49. i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  50. /* Verify if enabled */
  51. tmp_val = 0;
  52. i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  53. debug("DVI Encoder Read: 0x%02x\n", tmp_val);
  54. tmp_val = 0x10;
  55. i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  56. /* Verify if enabled */
  57. tmp_val = 0;
  58. i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  59. debug("DVI Encoder Read: 0x%02x\n", tmp_val);
  60. return 0;
  61. }
  62. int checkboard(void)
  63. {
  64. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  65. volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
  66. u8 *pixis_base = (u8 *)PIXIS_BASE;
  67. printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
  68. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  69. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  70. in_8(pixis_base + PIXIS_PVER));
  71. /*
  72. * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
  73. * bank and LBMAP=00 is the alternate bank. However, the pixis
  74. * altbank code can only set bits, not clear them, so we treat 00 as
  75. * the normal bank and 11 as the alternate.
  76. */
  77. switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
  78. case 0:
  79. puts("vBank: Standard\n");
  80. break;
  81. case 0x40:
  82. puts("Promjet\n");
  83. break;
  84. case 0x80:
  85. puts("NAND\n");
  86. break;
  87. case 0xC0:
  88. puts("vBank: Alternate\n");
  89. break;
  90. }
  91. mcm->abcr |= 0x00010000; /* 0 */
  92. mcm->hpmr3 = 0x80000008; /* 4c */
  93. mcm->hpmr0 = 0;
  94. mcm->hpmr1 = 0;
  95. mcm->hpmr2 = 0;
  96. mcm->hpmr4 = 0;
  97. mcm->hpmr5 = 0;
  98. return 0;
  99. }
  100. int dram_init(void)
  101. {
  102. phys_size_t dram_size = 0;
  103. #if defined(CONFIG_SPD_EEPROM)
  104. dram_size = fsl_ddr_sdram();
  105. #else
  106. dram_size = fixed_sdram();
  107. #endif
  108. setup_ddr_bat(dram_size);
  109. debug(" DDR: ");
  110. gd->ram_size = dram_size;
  111. return 0;
  112. }
  113. #if !defined(CONFIG_SPD_EEPROM)
  114. /*
  115. * Fixed sdram init -- doesn't use serial presence detect.
  116. */
  117. phys_size_t fixed_sdram(void)
  118. {
  119. #if !defined(CONFIG_SYS_RAMBOOT)
  120. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  121. struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
  122. uint d_init;
  123. ddr->cs0_bnds = 0x0000001f;
  124. ddr->cs0_config = 0x80010202;
  125. ddr->timing_cfg_3 = 0x00000000;
  126. ddr->timing_cfg_0 = 0x00260802;
  127. ddr->timing_cfg_1 = 0x3935d322;
  128. ddr->timing_cfg_2 = 0x14904cc8;
  129. ddr->sdram_mode = 0x00480432;
  130. ddr->sdram_mode_2 = 0x00000000;
  131. ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
  132. ddr->sdram_data_init = 0xDEADBEEF;
  133. ddr->sdram_clk_cntl = 0x03800000;
  134. ddr->sdram_cfg_2 = 0x04400010;
  135. #if defined(CONFIG_DDR_ECC)
  136. ddr->err_int_en = 0x0000000d;
  137. ddr->err_disable = 0x00000000;
  138. ddr->err_sbe = 0x00010000;
  139. #endif
  140. asm("sync;isync");
  141. udelay(500);
  142. ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
  143. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  144. d_init = 1;
  145. debug("DDR - 1st controller: memory initializing\n");
  146. /*
  147. * Poll until memory is initialized.
  148. * 512 Meg at 400 might hit this 200 times or so.
  149. */
  150. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
  151. udelay(1000);
  152. debug("DDR: memory initialized\n\n");
  153. asm("sync; isync");
  154. udelay(500);
  155. #endif
  156. return 512 * 1024 * 1024;
  157. #endif
  158. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  159. }
  160. #endif
  161. #if defined(CONFIG_PCI)
  162. /*
  163. * Initialize PCI Devices, report devices found.
  164. */
  165. #ifndef CONFIG_PCI_PNP
  166. static struct pci_config_table pci_fsl86xxads_config_table[] = {
  167. {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  168. PCI_IDSEL_NUMBER, PCI_ANY_ID,
  169. pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  170. PCI_ENET0_MEMADDR,
  171. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
  172. {}
  173. };
  174. #endif
  175. static struct pci_controller pci1_hose;
  176. #endif /* CONFIG_PCI */
  177. void pci_init_board(void)
  178. {
  179. volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
  180. volatile ccsr_gur_t *gur = &immap->im_gur;
  181. struct fsl_pci_info pci_info;
  182. u32 devdisr;
  183. int first_free_busno;
  184. int pci_agent;
  185. devdisr = in_be32(&gur->devdisr);
  186. first_free_busno = fsl_pcie_init_board(0);
  187. #ifdef CONFIG_PCI1
  188. if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
  189. SET_STD_PCI_INFO(pci_info, 1);
  190. set_next_law(pci_info.mem_phys,
  191. law_size_bits(pci_info.mem_size), pci_info.law);
  192. set_next_law(pci_info.io_phys,
  193. law_size_bits(pci_info.io_size), pci_info.law);
  194. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  195. printf("PCI: connected to PCI slots as %s" \
  196. " (base address %lx)\n",
  197. pci_agent ? "Agent" : "Host",
  198. pci_info.regs);
  199. #ifndef CONFIG_PCI_PNP
  200. pci1_hose.config_table = pci_mpc86xxcts_config_table;
  201. #endif
  202. first_free_busno = fsl_pci_init_port(&pci_info,
  203. &pci1_hose, first_free_busno);
  204. } else {
  205. printf("PCI: disabled\n");
  206. }
  207. puts("\n");
  208. #else
  209. setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
  210. #endif
  211. fsl_pcie_init_board(first_free_busno);
  212. }
  213. #if defined(CONFIG_OF_BOARD_SETUP)
  214. int ft_board_setup(void *blob, bd_t *bd)
  215. {
  216. ft_cpu_setup(blob, bd);
  217. FT_FSL_PCI_SETUP;
  218. return 0;
  219. }
  220. #endif
  221. /*
  222. * get_board_sys_clk
  223. * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
  224. */
  225. unsigned long
  226. get_board_sys_clk(ulong dummy)
  227. {
  228. u8 i;
  229. ulong val = 0;
  230. u8 *pixis_base = (u8 *)PIXIS_BASE;
  231. i = in_8(pixis_base + PIXIS_SPD);
  232. i &= 0x07;
  233. switch (i) {
  234. case 0:
  235. val = 33333000;
  236. break;
  237. case 1:
  238. val = 39999600;
  239. break;
  240. case 2:
  241. val = 49999500;
  242. break;
  243. case 3:
  244. val = 66666000;
  245. break;
  246. case 4:
  247. val = 83332500;
  248. break;
  249. case 5:
  250. val = 99999000;
  251. break;
  252. case 6:
  253. val = 133332000;
  254. break;
  255. case 7:
  256. val = 166665000;
  257. break;
  258. }
  259. return val;
  260. }
  261. int board_eth_init(bd_t *bis)
  262. {
  263. return pci_eth_init(bis);
  264. }
  265. void board_reset(void)
  266. {
  267. u8 *pixis_base = (u8 *)PIXIS_BASE;
  268. out_8(pixis_base + PIXIS_RST, 0);
  269. while (1)
  270. ;
  271. }