tlb.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <asm/mmu.h>
  10. struct fsl_e_tlb_entry tlb_table[] = {
  11. /* TLB 0 - for temp stack in cache */
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  13. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  14. 0, 0, BOOKE_PAGESZ_4K, 0),
  15. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. /*
  25. * TLB 0: 64M Non-cacheable, guarded
  26. * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
  27. * Out of reset this entry is only 4K.
  28. */
  29. SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
  30. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  31. 0, 0, BOOKE_PAGESZ_64M, 1),
  32. /*
  33. * TLB 1: 1G Non-cacheable, guarded
  34. * 0x80000000 1G PCIE 8,9,a,b
  35. */
  36. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
  37. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38. 0, 1, BOOKE_PAGESZ_1G, 1),
  39. /*
  40. * TLB 2: 256M Non-cacheable, guarded
  41. */
  42. SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
  43. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  44. 0, 2, BOOKE_PAGESZ_256M, 1),
  45. /*
  46. * TLB 3: 256M Non-cacheable, guarded
  47. */
  48. SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
  49. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50. 0, 3, BOOKE_PAGESZ_256M, 1),
  51. /*
  52. * TLB 4: 64M Non-cacheable, guarded
  53. * 0xe000_0000 1M CCSRBAR
  54. * 0xe100_0000 255M PCI IO range
  55. */
  56. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  57. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58. 0, 4, BOOKE_PAGESZ_64M, 1),
  59. /*
  60. * TLB 5: 64M Non-cacheable, guarded
  61. * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
  62. */
  63. SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
  64. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65. 0, 5, BOOKE_PAGESZ_64M, 1),
  66. };
  67. int num_tlb_entries = ARRAY_SIZE(tlb_table);