mpc8544ds.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <init.h>
  8. #include <pci.h>
  9. #include <asm/processor.h>
  10. #include <asm/mmu.h>
  11. #include <asm/immap_85xx.h>
  12. #include <asm/fsl_pci.h>
  13. #include <fsl_ddr_sdram.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/io.h>
  16. #include <miiphy.h>
  17. #include <linux/libfdt.h>
  18. #include <fdt_support.h>
  19. #include <fsl_mdio.h>
  20. #include <tsec.h>
  21. #include <netdev.h>
  22. #include "../common/sgmii_riser.h"
  23. int checkboard (void)
  24. {
  25. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  26. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  27. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  28. u8 vboot;
  29. u8 *pixis_base = (u8 *)PIXIS_BASE;
  30. if ((uint)&gur->porpllsr != 0xe00e0000) {
  31. printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  32. }
  33. printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
  34. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  35. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  36. in_8(pixis_base + PIXIS_PVER));
  37. vboot = in_8(pixis_base + PIXIS_VBOOT);
  38. if (vboot & PIXIS_VBOOT_FMAP)
  39. printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  40. else
  41. puts ("Promjet\n");
  42. lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
  43. lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
  44. ecm->eedr = 0xffffffff; /* Clear ecm errors */
  45. ecm->eeer = 0xffffffff; /* Enable ecm errors */
  46. return 0;
  47. }
  48. #ifdef CONFIG_PCI1
  49. static struct pci_controller pci1_hose;
  50. #endif
  51. #ifdef CONFIG_PCIE3
  52. static struct pci_controller pcie3_hose;
  53. #endif
  54. void pci_init_board(void)
  55. {
  56. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  57. struct fsl_pci_info pci_info;
  58. u32 devdisr, pordevsr, io_sel;
  59. u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
  60. int first_free_busno = 0;
  61. int pcie_ep, pcie_configured;
  62. devdisr = in_be32(&gur->devdisr);
  63. pordevsr = in_be32(&gur->pordevsr);
  64. porpllsr = in_be32(&gur->porpllsr);
  65. io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
  66. debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
  67. puts("\n");
  68. #ifdef CONFIG_PCIE3
  69. pcie_configured = is_serdes_configured(PCIE3);
  70. if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
  71. /* contains both PCIE3 MEM & IO space */
  72. set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
  73. LAW_TRGT_IF_PCIE_3);
  74. SET_STD_PCIE_INFO(pci_info, 3);
  75. pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
  76. /* outbound memory */
  77. pci_set_region(&pcie3_hose.regions[0],
  78. CONFIG_SYS_PCIE3_MEM_BUS2,
  79. CONFIG_SYS_PCIE3_MEM_PHYS2,
  80. CONFIG_SYS_PCIE3_MEM_SIZE2,
  81. PCI_REGION_MEM);
  82. pcie3_hose.region_count = 1;
  83. printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
  84. pcie_ep ? "Endpoint" : "Root Complex",
  85. pci_info.regs);
  86. first_free_busno = fsl_pci_init_port(&pci_info,
  87. &pcie3_hose, first_free_busno);
  88. /*
  89. * Activate ULI1575 legacy chip by performing a fake
  90. * memory access. Needed to make ULI RTC work.
  91. */
  92. in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
  93. } else {
  94. printf("PCIE3: disabled\n");
  95. }
  96. puts("\n");
  97. #else
  98. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
  99. #endif
  100. #ifdef CONFIG_PCIE1
  101. SET_STD_PCIE_INFO(pci_info, 1);
  102. first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
  103. #else
  104. setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
  105. #endif
  106. #ifdef CONFIG_PCIE2
  107. SET_STD_PCIE_INFO(pci_info, 2);
  108. first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
  109. #else
  110. setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
  111. #endif
  112. #ifdef CONFIG_PCI1
  113. pci_speed = 66666000;
  114. pci_32 = 1;
  115. pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  116. pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  117. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  118. SET_STD_PCI_INFO(pci_info, 1);
  119. set_next_law(pci_info.mem_phys,
  120. law_size_bits(pci_info.mem_size), pci_info.law);
  121. set_next_law(pci_info.io_phys,
  122. law_size_bits(pci_info.io_size), pci_info.law);
  123. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  124. printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  125. (pci_32) ? 32 : 64,
  126. (pci_speed == 33333000) ? "33" :
  127. (pci_speed == 66666000) ? "66" : "unknown",
  128. pci_clk_sel ? "sync" : "async",
  129. pci_agent ? "agent" : "host",
  130. pci_arb ? "arbiter" : "external-arbiter",
  131. pci_info.regs);
  132. first_free_busno = fsl_pci_init_port(&pci_info,
  133. &pci1_hose, first_free_busno);
  134. } else {
  135. printf("PCI: disabled\n");
  136. }
  137. puts("\n");
  138. #else
  139. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  140. #endif
  141. }
  142. int last_stage_init(void)
  143. {
  144. return 0;
  145. }
  146. unsigned long
  147. get_board_sys_clk(ulong dummy)
  148. {
  149. u8 i, go_bit, rd_clks;
  150. ulong val = 0;
  151. u8 *pixis_base = (u8 *)PIXIS_BASE;
  152. go_bit = in_8(pixis_base + PIXIS_VCTL);
  153. go_bit &= 0x01;
  154. rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
  155. rd_clks &= 0x1C;
  156. /*
  157. * Only if both go bit and the SCLK bit in VCFGEN0 are set
  158. * should we be using the AUX register. Remember, we also set the
  159. * GO bit to boot from the alternate bank on the on-board flash
  160. */
  161. if (go_bit) {
  162. if (rd_clks == 0x1c)
  163. i = in_8(pixis_base + PIXIS_AUX);
  164. else
  165. i = in_8(pixis_base + PIXIS_SPD);
  166. } else {
  167. i = in_8(pixis_base + PIXIS_SPD);
  168. }
  169. i &= 0x07;
  170. switch (i) {
  171. case 0:
  172. val = 33333333;
  173. break;
  174. case 1:
  175. val = 40000000;
  176. break;
  177. case 2:
  178. val = 50000000;
  179. break;
  180. case 3:
  181. val = 66666666;
  182. break;
  183. case 4:
  184. val = 83000000;
  185. break;
  186. case 5:
  187. val = 100000000;
  188. break;
  189. case 6:
  190. val = 133333333;
  191. break;
  192. case 7:
  193. val = 166666666;
  194. break;
  195. }
  196. return val;
  197. }
  198. #define MIIM_CIS8204_SLED_CON 0x1b
  199. #define MIIM_CIS8204_SLEDCON_INIT 0x1115
  200. /*
  201. * Hack to write all 4 PHYs with the LED values
  202. */
  203. int board_phy_config(struct phy_device *phydev)
  204. {
  205. static int do_once;
  206. uint phyid;
  207. struct mii_dev *bus = phydev->bus;
  208. if (phydev->drv->config)
  209. phydev->drv->config(phydev);
  210. if (do_once)
  211. return 0;
  212. for (phyid = 0; phyid < 4; phyid++)
  213. bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
  214. MIIM_CIS8204_SLEDCON_INIT);
  215. do_once = 1;
  216. return 0;
  217. }
  218. int board_eth_init(bd_t *bis)
  219. {
  220. #ifdef CONFIG_TSEC_ENET
  221. struct fsl_pq_mdio_info mdio_info;
  222. struct tsec_info_struct tsec_info[2];
  223. int num = 0;
  224. #ifdef CONFIG_TSEC1
  225. SET_STD_TSEC_INFO(tsec_info[num], 1);
  226. if (is_serdes_configured(SGMII_TSEC1)) {
  227. puts("eTSEC1 is in sgmii mode.\n");
  228. tsec_info[num].flags |= TSEC_SGMII;
  229. }
  230. num++;
  231. #endif
  232. #ifdef CONFIG_TSEC3
  233. SET_STD_TSEC_INFO(tsec_info[num], 3);
  234. if (is_serdes_configured(SGMII_TSEC3)) {
  235. puts("eTSEC3 is in sgmii mode.\n");
  236. tsec_info[num].flags |= TSEC_SGMII;
  237. }
  238. num++;
  239. #endif
  240. if (!num) {
  241. printf("No TSECs initialized\n");
  242. return 0;
  243. }
  244. if (is_serdes_configured(SGMII_TSEC1) ||
  245. is_serdes_configured(SGMII_TSEC3)) {
  246. fsl_sgmii_riser_init(tsec_info, num);
  247. }
  248. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  249. mdio_info.name = DEFAULT_MII_NAME;
  250. fsl_pq_mdio_init(bis, &mdio_info);
  251. tsec_eth_init(bis, tsec_info, num);
  252. #endif
  253. return pci_eth_init(bis);
  254. }
  255. #if defined(CONFIG_OF_BOARD_SETUP)
  256. int ft_board_setup(void *blob, bd_t *bd)
  257. {
  258. ft_cpu_setup(blob, bd);
  259. FT_FSL_PCI_SETUP;
  260. #ifdef CONFIG_FSL_SGMII_RISER
  261. fsl_sgmii_riser_fdt_fixup(blob);
  262. #endif
  263. return 0;
  264. }
  265. #endif