pci.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <mpc83xx.h>
  8. #include <pci.h>
  9. #include <asm/io.h>
  10. static struct pci_region pci_regions[] = {
  11. {
  12. bus_start: CONFIG_SYS_PCI_MEM_BASE,
  13. phys_start: CONFIG_SYS_PCI_MEM_PHYS,
  14. size: CONFIG_SYS_PCI_MEM_SIZE,
  15. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  16. },
  17. {
  18. bus_start: CONFIG_SYS_PCI_MMIO_BASE,
  19. phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
  20. size: CONFIG_SYS_PCI_MMIO_SIZE,
  21. flags: PCI_REGION_MEM
  22. },
  23. {
  24. bus_start: CONFIG_SYS_PCI_IO_BASE,
  25. phys_start: CONFIG_SYS_PCI_IO_PHYS,
  26. size: CONFIG_SYS_PCI_IO_SIZE,
  27. flags: PCI_REGION_IO
  28. }
  29. };
  30. static struct pci_region pcie_regions_0[] = {
  31. {
  32. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  33. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  34. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  35. .flags = PCI_REGION_MEM,
  36. },
  37. {
  38. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  39. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  40. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  41. .flags = PCI_REGION_IO,
  42. },
  43. };
  44. static struct pci_region pcie_regions_1[] = {
  45. {
  46. .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
  47. .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
  48. .size = CONFIG_SYS_PCIE2_MEM_SIZE,
  49. .flags = PCI_REGION_MEM,
  50. },
  51. {
  52. .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
  53. .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
  54. .size = CONFIG_SYS_PCIE2_IO_SIZE,
  55. .flags = PCI_REGION_IO,
  56. },
  57. };
  58. void pci_init_board(void)
  59. {
  60. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  61. volatile sysconf83xx_t *sysconf = &immr->sysconf;
  62. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  63. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  64. volatile law83xx_t *pcie_law = sysconf->pcielaw;
  65. struct pci_region *reg[] = { pci_regions };
  66. struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
  67. u32 spridr = in_be32(&immr->sysconf.spridr);
  68. /* Enable all 5 PCI_CLK_OUTPUTS */
  69. clk->occr |= 0xf8000000;
  70. udelay(2000);
  71. /* Configure PCI Local Access Windows */
  72. pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
  73. pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  74. pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
  75. pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  76. mpc83xx_pci_init(1, reg);
  77. /* There is no PEX in MPC8379 parts. */
  78. if (PARTID_NO_E(spridr) == SPR_8379)
  79. return;
  80. /* Configure the clock for PCIE controller */
  81. clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
  82. SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
  83. /* Deassert the resets in the control register */
  84. out_be32(&sysconf->pecr1, 0xE0008000);
  85. out_be32(&sysconf->pecr2, 0xE0008000);
  86. udelay(2000);
  87. /* Configure PCI Express Local Access Windows */
  88. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  89. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  90. out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
  91. out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
  92. mpc83xx_pcie_init(2, pcie_reg);
  93. }