mpc8349itx.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. */
  5. #include <common.h>
  6. #include <ioports.h>
  7. #include <mpc83xx.h>
  8. #include <i2c.h>
  9. #include <miiphy.h>
  10. #include <vsc7385.h>
  11. #ifdef CONFIG_PCI
  12. #include <asm/mpc8349_pci.h>
  13. #include <pci.h>
  14. #endif
  15. #include <spd_sdram.h>
  16. #include <asm/mmu.h>
  17. #if defined(CONFIG_OF_LIBFDT)
  18. #include <linux/libfdt.h>
  19. #endif
  20. #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
  21. #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #ifndef CONFIG_SPD_EEPROM
  24. /*************************************************************************
  25. * fixed sdram init -- doesn't use serial presence detect.
  26. ************************************************************************/
  27. int fixed_sdram(void)
  28. {
  29. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  30. /* The size of RAM, in bytes */
  31. u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
  32. u32 ddr_size_log2 = __ilog2(ddr_size);
  33. im->sysconf.ddrlaw[0].ar =
  34. LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  35. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  36. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  37. #warning Chip select bounds is only configurable in 16MB increments
  38. #endif
  39. im->ddr.csbnds[0].csbnds =
  40. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  41. (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  42. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  43. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  44. /* Only one CS for DDR */
  45. im->ddr.cs_config[1] = 0;
  46. im->ddr.cs_config[2] = 0;
  47. im->ddr.cs_config[3] = 0;
  48. debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
  49. debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
  50. debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
  51. debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
  52. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  53. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
  54. im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
  55. im->ddr.sdram_mode =
  56. (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
  57. im->ddr.sdram_interval =
  58. (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
  59. SDRAM_INTERVAL_BSTOPRE_SHIFT);
  60. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  61. udelay(200);
  62. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  63. debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
  64. debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
  65. debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
  66. debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
  67. debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
  68. return CONFIG_SYS_DDR_SIZE;
  69. }
  70. #endif
  71. #ifdef CONFIG_PCI
  72. /*
  73. * Initialize PCI Devices, report devices found
  74. */
  75. #ifndef CONFIG_PCI_PNP
  76. static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
  77. {
  78. PCI_ANY_ID,
  79. PCI_ANY_ID,
  80. PCI_ANY_ID,
  81. PCI_ANY_ID,
  82. 0x0f,
  83. PCI_ANY_ID,
  84. pci_cfgfunc_config_device,
  85. {
  86. PCI_ENET0_IOADDR,
  87. PCI_ENET0_MEMADDR,
  88. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
  89. },
  90. {}
  91. }
  92. #endif
  93. volatile static struct pci_controller hose[] = {
  94. {
  95. #ifndef CONFIG_PCI_PNP
  96. config_table:pci_mpc83xxmitx_config_table,
  97. #endif
  98. },
  99. {
  100. #ifndef CONFIG_PCI_PNP
  101. config_table:pci_mpc83xxmitx_config_table,
  102. #endif
  103. }
  104. };
  105. #endif /* CONFIG_PCI */
  106. int dram_init(void)
  107. {
  108. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  109. u32 msize = 0;
  110. #ifdef CONFIG_DDR_ECC
  111. volatile ddr83xx_t *ddr = &im->ddr;
  112. #endif
  113. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  114. return -ENXIO;
  115. /* DDR SDRAM - Main SODIMM */
  116. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  117. #ifdef CONFIG_SPD_EEPROM
  118. msize = spd_sdram();
  119. #else
  120. msize = fixed_sdram();
  121. #endif
  122. #ifdef CONFIG_DDR_ECC
  123. if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
  124. /* Unlike every other board, on the 83xx spd_sdram() returns
  125. megabytes instead of just bytes. That's why we need to
  126. multiple by 1MB when calling ddr_enable_ecc(). */
  127. ddr_enable_ecc(msize * 1048576);
  128. #endif
  129. /* return total bus RAM size(bytes) */
  130. gd->ram_size = msize * 1024 * 1024;
  131. return 0;
  132. }
  133. int checkboard(void)
  134. {
  135. #ifdef CONFIG_TARGET_MPC8349ITX
  136. puts("Board: Freescale MPC8349E-mITX\n");
  137. #else
  138. puts("Board: Freescale MPC8349E-mITX-GP\n");
  139. #endif
  140. return 0;
  141. }
  142. /*
  143. * Implement a work-around for a hardware problem with compact
  144. * flash.
  145. *
  146. * Program the UPM if compact flash is enabled.
  147. */
  148. int misc_init_f(void)
  149. {
  150. #ifdef CONFIG_VSC7385_ENET
  151. volatile u32 *vsc7385_cpuctrl;
  152. /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
  153. default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
  154. means it is 0 when the IRQ is not active. This makes the wire-AND
  155. logic always assert IRQ7 to CPU even if there is no request from the
  156. switch. Since the compact flash and the switch share the same IRQ,
  157. the Linux kernel will think that the compact flash is requesting irq
  158. and get stuck when it tries to clear the IRQ. Thus we need to set
  159. the L2_IRQ0 and L2_IRQ1 to active low.
  160. The following code sets the L1_IRQ and L2_IRQ polarity to active low.
  161. Without this code, compact flash will not work in Linux because
  162. unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
  163. don't enable compact flash for U-Boot.
  164. */
  165. vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
  166. *vsc7385_cpuctrl |= 0x0c;
  167. #endif
  168. #ifdef CONFIG_COMPACT_FLASH
  169. /* UPM Table Configuration Code */
  170. static uint UPMATable[] = {
  171. 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
  172. 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
  173. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  174. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  175. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
  176. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  177. 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
  178. 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
  179. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  180. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  181. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  182. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  183. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  184. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  185. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  186. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
  187. };
  188. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  189. set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  190. set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
  191. /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
  192. GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
  193. */
  194. immap->im_lbc.mamr = 0x08404440;
  195. upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
  196. puts("UPMA: Configured for compact flash\n");
  197. #endif
  198. return 0;
  199. }
  200. /*
  201. * Miscellaneous late-boot configurations
  202. *
  203. * Make sure the EEPROM has the HRCW correctly programmed.
  204. * Make sure the RTC is correctly programmed.
  205. *
  206. * The MPC8349E-mITX can be configured to load the HRCW from
  207. * EEPROM instead of flash. This is controlled via jumpers
  208. * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
  209. * jumpered), but if they're set to 001 or 010, then the HRCW is
  210. * read from the "I2C EEPROM".
  211. *
  212. * This function makes sure that the I2C EEPROM is programmed
  213. * correctly.
  214. *
  215. * If a VSC7385 microcode image is present, then upload it.
  216. */
  217. int misc_init_r(void)
  218. {
  219. int rc = 0;
  220. #if defined(CONFIG_SYS_I2C)
  221. unsigned int orig_bus = i2c_get_bus_num();
  222. u8 i2c_data;
  223. #ifdef CONFIG_SYS_I2C_RTC_ADDR
  224. u8 ds1339_data[17];
  225. #endif
  226. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
  227. static u8 eeprom_data[] = /* HRCW data */
  228. {
  229. 0xAA, 0x55, 0xAA, /* Preamble */
  230. 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
  231. 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
  232. (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
  233. (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
  234. (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
  235. CONFIG_SYS_HRCW_LOW & 0xFF,
  236. 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
  237. 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
  238. (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
  239. (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
  240. (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
  241. CONFIG_SYS_HRCW_HIGH & 0xFF
  242. };
  243. u8 data[sizeof(eeprom_data)];
  244. #endif
  245. printf("Board revision: ");
  246. i2c_set_bus_num(1);
  247. if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
  248. printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
  249. else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
  250. printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
  251. else {
  252. printf("Unknown\n");
  253. rc = 1;
  254. }
  255. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
  256. i2c_set_bus_num(0);
  257. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
  258. if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
  259. if (i2c_write
  260. (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
  261. sizeof(eeprom_data)) != 0) {
  262. puts("Failure writing the HRCW to EEPROM via I2C.\n");
  263. rc = 1;
  264. }
  265. }
  266. } else {
  267. puts("Failure reading the HRCW from EEPROM via I2C.\n");
  268. rc = 1;
  269. }
  270. #endif
  271. #ifdef CONFIG_SYS_I2C_RTC_ADDR
  272. i2c_set_bus_num(1);
  273. if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
  274. == 0) {
  275. /* Work-around for MPC8349E-mITX bug #13601.
  276. If the RTC does not contain valid register values, the DS1339
  277. Linux driver will not work.
  278. */
  279. /* Make sure status register bits 6-2 are zero */
  280. ds1339_data[0x0f] &= ~0x7c;
  281. /* Check for a valid day register value */
  282. ds1339_data[0x03] &= ~0xf8;
  283. if (ds1339_data[0x03] == 0) {
  284. ds1339_data[0x03] = 1;
  285. }
  286. /* Check for a valid date register value */
  287. ds1339_data[0x04] &= ~0xc0;
  288. if ((ds1339_data[0x04] == 0) ||
  289. ((ds1339_data[0x04] & 0x0f) > 9) ||
  290. (ds1339_data[0x04] >= 0x32)) {
  291. ds1339_data[0x04] = 1;
  292. }
  293. /* Check for a valid month register value */
  294. ds1339_data[0x05] &= ~0x60;
  295. if ((ds1339_data[0x05] == 0) ||
  296. ((ds1339_data[0x05] & 0x0f) > 9) ||
  297. ((ds1339_data[0x05] >= 0x13)
  298. && (ds1339_data[0x05] <= 0x19))) {
  299. ds1339_data[0x05] = 1;
  300. }
  301. /* Enable Oscillator and rate select */
  302. ds1339_data[0x0e] = 0x1c;
  303. /* Work-around for MPC8349E-mITX bug #13330.
  304. Ensure that the RTC control register contains the value 0x1c.
  305. This affects SATA performance.
  306. */
  307. if (i2c_write
  308. (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
  309. sizeof(ds1339_data))) {
  310. puts("Failure writing to the RTC via I2C.\n");
  311. rc = 1;
  312. }
  313. } else {
  314. puts("Failure reading from the RTC via I2C.\n");
  315. rc = 1;
  316. }
  317. #endif
  318. i2c_set_bus_num(orig_bus);
  319. #endif
  320. #ifdef CONFIG_VSC7385_IMAGE
  321. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  322. CONFIG_VSC7385_IMAGE_SIZE)) {
  323. puts("Failure uploading VSC7385 microcode.\n");
  324. rc = 1;
  325. }
  326. #endif
  327. return rc;
  328. }
  329. #if defined(CONFIG_OF_BOARD_SETUP)
  330. int ft_board_setup(void *blob, bd_t *bd)
  331. {
  332. ft_cpu_setup(blob, bd);
  333. #ifdef CONFIG_PCI
  334. ft_pci_setup(blob, bd);
  335. #endif
  336. return 0;
  337. }
  338. #endif