sdram.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. *
  5. * Authors: Nick.Spence@freescale.com
  6. * Wilson.Lo@freescale.com
  7. * scottwood@freescale.com
  8. */
  9. #include <common.h>
  10. #include <mpc83xx.h>
  11. #include <spd_sdram.h>
  12. #include <asm/bitops.h>
  13. #include <asm/io.h>
  14. #include <asm/processor.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. static void resume_from_sleep(void)
  17. {
  18. u32 magic = *(u32 *)0;
  19. typedef void (*func_t)(void);
  20. func_t resume = *(func_t *)4;
  21. if (magic == 0xf5153ae5)
  22. resume();
  23. gd->flags &= ~GD_FLG_SILENT;
  24. puts("\nResume from sleep failed: bad magic word\n");
  25. }
  26. /* Fixed sdram init -- doesn't use serial presence detect.
  27. *
  28. * This is useful for faster booting in configs where the RAM is unlikely
  29. * to be changed, or for things like NAND booting where space is tight.
  30. */
  31. #ifndef CONFIG_SYS_RAMBOOT
  32. static long fixed_sdram(void)
  33. {
  34. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  35. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  36. u32 msize_log2 = __ilog2(msize);
  37. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  38. im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  39. im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  40. /*
  41. * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  42. * or the DDR2 controller may fail to initialize correctly.
  43. */
  44. __udelay(50000);
  45. im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
  46. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  47. /* Currently we use only one CS, so disable the other bank. */
  48. im->ddr.cs_config[1] = 0;
  49. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  50. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  51. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  52. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  53. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  54. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  55. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
  56. else
  57. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  58. im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  59. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  60. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  61. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  62. sync();
  63. /* enable DDR controller */
  64. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  65. sync();
  66. return msize;
  67. }
  68. #else
  69. static long fixed_sdram(void)
  70. {
  71. return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  72. }
  73. #endif /* CONFIG_SYS_RAMBOOT */
  74. int dram_init(void)
  75. {
  76. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  77. u32 msize;
  78. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  79. return -ENXIO;
  80. /* DDR SDRAM */
  81. msize = fixed_sdram();
  82. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  83. resume_from_sleep();
  84. /* set total bus SDRAM size(bytes) -- DDR */
  85. gd->ram_size = msize;
  86. return 0;
  87. }