mpc8315erdb.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. * Dave Liu <daveliu@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <hwconfig.h>
  10. #include <i2c.h>
  11. #include <init.h>
  12. #include <linux/libfdt.h>
  13. #include <fdt_support.h>
  14. #include <pci.h>
  15. #include <mpc83xx.h>
  16. #include <netdev.h>
  17. #include <asm/io.h>
  18. #include <ns16550.h>
  19. #include <nand.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int board_early_init_f(void)
  22. {
  23. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  24. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  25. gd->flags |= GD_FLG_SILENT;
  26. return 0;
  27. }
  28. #ifndef CONFIG_NAND_SPL
  29. static u8 read_board_info(void)
  30. {
  31. u8 val8;
  32. i2c_set_bus_num(0);
  33. if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
  34. return val8;
  35. else
  36. return 0;
  37. }
  38. int checkboard(void)
  39. {
  40. static const char * const rev_str[] = {
  41. "0.0",
  42. "0.1",
  43. "1.0",
  44. "1.1",
  45. "<unknown>",
  46. };
  47. u8 info;
  48. int i;
  49. info = read_board_info();
  50. i = (!info) ? 4: info & 0x03;
  51. printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
  52. return 0;
  53. }
  54. static struct pci_region pci_regions[] = {
  55. {
  56. bus_start: CONFIG_SYS_PCI_MEM_BASE,
  57. phys_start: CONFIG_SYS_PCI_MEM_PHYS,
  58. size: CONFIG_SYS_PCI_MEM_SIZE,
  59. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  60. },
  61. {
  62. bus_start: CONFIG_SYS_PCI_MMIO_BASE,
  63. phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
  64. size: CONFIG_SYS_PCI_MMIO_SIZE,
  65. flags: PCI_REGION_MEM
  66. },
  67. {
  68. bus_start: CONFIG_SYS_PCI_IO_BASE,
  69. phys_start: CONFIG_SYS_PCI_IO_PHYS,
  70. size: CONFIG_SYS_PCI_IO_SIZE,
  71. flags: PCI_REGION_IO
  72. }
  73. };
  74. static struct pci_region pcie_regions_0[] = {
  75. {
  76. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  77. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  78. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  79. .flags = PCI_REGION_MEM,
  80. },
  81. {
  82. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  83. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  84. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  85. .flags = PCI_REGION_IO,
  86. },
  87. };
  88. static struct pci_region pcie_regions_1[] = {
  89. {
  90. .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
  91. .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
  92. .size = CONFIG_SYS_PCIE2_MEM_SIZE,
  93. .flags = PCI_REGION_MEM,
  94. },
  95. {
  96. .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
  97. .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
  98. .size = CONFIG_SYS_PCIE2_IO_SIZE,
  99. .flags = PCI_REGION_IO,
  100. },
  101. };
  102. void pci_init_board(void)
  103. {
  104. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  105. volatile sysconf83xx_t *sysconf = &immr->sysconf;
  106. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  107. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  108. volatile law83xx_t *pcie_law = sysconf->pcielaw;
  109. struct pci_region *reg[] = { pci_regions };
  110. struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
  111. /* Enable all 3 PCI_CLK_OUTPUTs. */
  112. clk->occr |= 0xe0000000;
  113. /*
  114. * Configure PCI Local Access Windows
  115. */
  116. pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
  117. pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  118. pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
  119. pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  120. mpc83xx_pci_init(1, reg);
  121. /* Configure the clock for PCIE controller */
  122. clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
  123. SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
  124. /* Deassert the resets in the control register */
  125. out_be32(&sysconf->pecr1, 0xE0008000);
  126. out_be32(&sysconf->pecr2, 0xE0008000);
  127. udelay(2000);
  128. /* Configure PCI Express Local Access Windows */
  129. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  130. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  131. out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
  132. out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
  133. mpc83xx_pcie_init(2, pcie_reg);
  134. }
  135. #if defined(CONFIG_OF_BOARD_SETUP)
  136. void fdt_tsec1_fixup(void *fdt, bd_t *bd)
  137. {
  138. const char disabled[] = "disabled";
  139. const char *path;
  140. int ret;
  141. if (hwconfig_arg_cmp("board_type", "tsec1")) {
  142. return;
  143. } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
  144. printf("NOTICE: No or unknown board_type hwconfig specified.\n"
  145. " Assuming board with TSEC1.\n");
  146. return;
  147. }
  148. ret = fdt_path_offset(fdt, "/aliases");
  149. if (ret < 0) {
  150. printf("WARNING: can't find /aliases node\n");
  151. return;
  152. }
  153. path = fdt_getprop(fdt, ret, "ethernet0", NULL);
  154. if (!path) {
  155. printf("WARNING: can't find ethernet0 alias\n");
  156. return;
  157. }
  158. do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
  159. }
  160. int ft_board_setup(void *blob, bd_t *bd)
  161. {
  162. ft_cpu_setup(blob, bd);
  163. #ifdef CONFIG_PCI
  164. ft_pci_setup(blob, bd);
  165. #endif
  166. fsl_fdt_fixup_dr_usb(blob, bd);
  167. fdt_tsec1_fixup(blob, bd);
  168. return 0;
  169. }
  170. #endif
  171. int board_eth_init(bd_t *bis)
  172. {
  173. cpu_eth_init(bis); /* Initialize TSECs first */
  174. return pci_eth_init(bis);
  175. }
  176. #else /* CONFIG_NAND_SPL */
  177. int checkboard(void)
  178. {
  179. puts("Board: Freescale MPC8315ERDB\n");
  180. return 0;
  181. }
  182. void board_init_f(ulong bootflag)
  183. {
  184. board_early_init_f();
  185. NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
  186. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  187. puts("NAND boot... ");
  188. timer_init();
  189. dram_init();
  190. relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
  191. CONFIG_SYS_NAND_U_BOOT_RELOC);
  192. }
  193. void board_init_r(gd_t *gd, ulong dest_addr)
  194. {
  195. nand_boot();
  196. }
  197. void putc(char c)
  198. {
  199. if (gd->flags & GD_FLG_SILENT)
  200. return;
  201. if (c == '\n')
  202. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
  203. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
  204. }
  205. #endif /* CONFIG_NAND_SPL */