sdram.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
  4. *
  5. * Authors: Nick.Spence@freescale.com
  6. * Wilson.Lo@freescale.com
  7. * scottwood@freescale.com
  8. */
  9. #include <common.h>
  10. #include <mpc83xx.h>
  11. #include <spd_sdram.h>
  12. #include <asm/bitops.h>
  13. #include <asm/io.h>
  14. #include <asm/processor.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  17. static void resume_from_sleep(void)
  18. {
  19. u32 magic = *(u32 *)0;
  20. typedef void (*func_t)(void);
  21. func_t resume = *(func_t *)4;
  22. if (magic == 0xf5153ae5)
  23. resume();
  24. gd->flags &= ~GD_FLG_SILENT;
  25. puts("\nResume from sleep failed: bad magic word\n");
  26. }
  27. #endif
  28. /* Fixed sdram init -- doesn't use serial presence detect.
  29. *
  30. * This is useful for faster booting in configs where the RAM is unlikely
  31. * to be changed, or for things like NAND booting where space is tight.
  32. */
  33. static long fixed_sdram(void)
  34. {
  35. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  36. #ifndef CONFIG_SYS_RAMBOOT
  37. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  38. u32 msize_log2 = __ilog2(msize);
  39. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  40. im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  41. im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  42. /*
  43. * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  44. * or the DDR2 controller may fail to initialize correctly.
  45. */
  46. __udelay(50000);
  47. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  48. #warning Chip select bounds is only configurable in 16MB increments
  49. #endif
  50. im->ddr.csbnds[0].csbnds =
  51. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  52. (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
  53. CSBNDS_EA);
  54. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  55. /* Currently we use only one CS, so disable the other bank. */
  56. im->ddr.cs_config[1] = 0;
  57. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  58. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  59. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  60. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  61. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  62. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  63. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  64. im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
  65. else
  66. #endif
  67. im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
  68. im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
  69. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  70. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
  71. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  72. sync();
  73. /* enable DDR controller */
  74. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  75. #endif
  76. return msize;
  77. }
  78. int dram_init(void)
  79. {
  80. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  81. volatile fsl_lbc_t *lbc = &im->im_lbc;
  82. u32 msize;
  83. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  84. return -ENXIO;
  85. /* DDR SDRAM - Main SODIMM */
  86. msize = fixed_sdram();
  87. /* Local Bus setup lbcr and mrtpr */
  88. lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
  89. /* LB refresh timer prescal, 266MHz/32 */
  90. lbc->mrtpr = 0x20000000;
  91. sync();
  92. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  93. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  94. resume_from_sleep();
  95. #endif
  96. /* return total bus SDRAM size(bytes) -- DDR */
  97. gd->ram_size = msize;
  98. return 0;
  99. }