mpc8313erdb.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #if defined(CONFIG_OF_LIBFDT)
  10. #include <linux/libfdt.h>
  11. #endif
  12. #include <pci.h>
  13. #include <mpc83xx.h>
  14. #include <vsc7385.h>
  15. #include <ns16550.h>
  16. #include <nand.h>
  17. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  18. #include <asm/gpio.h>
  19. #endif
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int board_early_init_f(void)
  22. {
  23. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  24. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  25. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  26. gd->flags |= GD_FLG_SILENT;
  27. #endif
  28. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  29. mpc83xx_gpio_init_f();
  30. #endif
  31. return 0;
  32. }
  33. int board_early_init_r(void)
  34. {
  35. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  36. mpc83xx_gpio_init_r();
  37. #endif
  38. return 0;
  39. }
  40. int checkboard(void)
  41. {
  42. puts("Board: Freescale MPC8313ERDB\n");
  43. return 0;
  44. }
  45. #ifndef CONFIG_SPL_BUILD
  46. static struct pci_region pci_regions[] = {
  47. {
  48. .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
  49. .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
  50. .size = CONFIG_SYS_PCI1_MEM_SIZE,
  51. .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
  52. },
  53. {
  54. .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
  55. .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
  56. .size = CONFIG_SYS_PCI1_MMIO_SIZE,
  57. .flags = PCI_REGION_MEM
  58. },
  59. {
  60. .bus_start = CONFIG_SYS_PCI1_IO_BASE,
  61. .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
  62. .size = CONFIG_SYS_PCI1_IO_SIZE,
  63. .flags = PCI_REGION_IO
  64. }
  65. };
  66. void pci_init_board(void)
  67. {
  68. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  69. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  70. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  71. struct pci_region *reg[] = { pci_regions };
  72. /* Enable all 3 PCI_CLK_OUTPUTs. */
  73. clk->occr |= 0xe0000000;
  74. /*
  75. * Configure PCI Local Access Windows
  76. */
  77. pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  78. pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  79. pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  80. pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  81. mpc83xx_pci_init(1, reg);
  82. }
  83. /*
  84. * Miscellaneous late-boot configurations
  85. *
  86. * If a VSC7385 microcode image is present, then upload it.
  87. */
  88. int misc_init_r(void)
  89. {
  90. int rc = 0;
  91. #ifdef CONFIG_VSC7385_IMAGE
  92. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  93. CONFIG_VSC7385_IMAGE_SIZE)) {
  94. puts("Failure uploading VSC7385 microcode.\n");
  95. rc = 1;
  96. }
  97. #endif
  98. return rc;
  99. }
  100. #if defined(CONFIG_OF_BOARD_SETUP)
  101. int ft_board_setup(void *blob, bd_t *bd)
  102. {
  103. ft_cpu_setup(blob, bd);
  104. #ifdef CONFIG_PCI
  105. ft_pci_setup(blob, bd);
  106. #endif
  107. return 0;
  108. }
  109. #endif
  110. #else /* CONFIG_SPL_BUILD */
  111. void board_init_f(ulong bootflag)
  112. {
  113. board_early_init_f();
  114. NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
  115. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  116. puts("NAND boot... ");
  117. timer_init();
  118. dram_init();
  119. relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
  120. CONFIG_SYS_NAND_U_BOOT_RELOC);
  121. }
  122. void board_init_r(gd_t *gd, ulong dest_addr)
  123. {
  124. nand_boot();
  125. }
  126. void putc(char c)
  127. {
  128. if (gd->flags & GD_FLG_SILENT)
  129. return;
  130. if (c == '\n')
  131. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
  132. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
  133. }
  134. #endif