m54418twr.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  4. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  5. */
  6. #include <common.h>
  7. #include <spi.h>
  8. #include <asm/io.h>
  9. #include <asm/immap.h>
  10. #include <mmc.h>
  11. #include <fsl_esdhc_imx.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. int checkboard(void)
  14. {
  15. /*
  16. * need to to:
  17. * Check serial flash size. if 2mb evb, else 8mb demo
  18. */
  19. puts("Board: ");
  20. puts("Freescale MCF54418 Tower System\n");
  21. return 0;
  22. };
  23. int dram_init(void)
  24. {
  25. u32 dramsize;
  26. #if defined(CONFIG_SERIAL_BOOT)
  27. /*
  28. * Serial Boot: The dram is already initialized in start.S
  29. * only require to return DRAM size
  30. */
  31. dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  32. #else
  33. sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
  34. ccm_t *ccm = (ccm_t *)MMAP_CCM;
  35. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  36. pm_t *pm = (pm_t *) MMAP_PM;
  37. u32 i;
  38. dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  39. for (i = 0x13; i < 0x20; i++) {
  40. if (dramsize == (1 << i))
  41. break;
  42. }
  43. out_8(&pm->pmcr0, 0x2E);
  44. out_8(&gpio->mscr_sdram, 1);
  45. clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
  46. setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
  47. out_be32(&sdram->rcrcr, 0x40000000);
  48. out_be32(&sdram->padcr, 0x01030203);
  49. out_be32(&sdram->cr00, 0x01010101);
  50. out_be32(&sdram->cr01, 0x00000101);
  51. out_be32(&sdram->cr02, 0x01010100);
  52. out_be32(&sdram->cr03, 0x01010000);
  53. out_be32(&sdram->cr04, 0x00010101);
  54. out_be32(&sdram->cr06, 0x00010100);
  55. out_be32(&sdram->cr07, 0x00000001);
  56. out_be32(&sdram->cr08, 0x01000001);
  57. out_be32(&sdram->cr09, 0x00000100);
  58. out_be32(&sdram->cr10, 0x00010001);
  59. out_be32(&sdram->cr11, 0x00000200);
  60. out_be32(&sdram->cr12, 0x01000002);
  61. out_be32(&sdram->cr13, 0x00000000);
  62. out_be32(&sdram->cr14, 0x00000100);
  63. out_be32(&sdram->cr15, 0x02000100);
  64. out_be32(&sdram->cr16, 0x02000407);
  65. out_be32(&sdram->cr17, 0x02030007);
  66. out_be32(&sdram->cr18, 0x02000100);
  67. out_be32(&sdram->cr19, 0x0A030203);
  68. out_be32(&sdram->cr20, 0x00020708);
  69. out_be32(&sdram->cr21, 0x00050008);
  70. out_be32(&sdram->cr22, 0x04030002);
  71. out_be32(&sdram->cr23, 0x00000004);
  72. out_be32(&sdram->cr24, 0x020A0000);
  73. out_be32(&sdram->cr25, 0x0C00000E);
  74. out_be32(&sdram->cr26, 0x00002004);
  75. out_be32(&sdram->cr28, 0x00100010);
  76. out_be32(&sdram->cr29, 0x00100010);
  77. out_be32(&sdram->cr31, 0x07990000);
  78. out_be32(&sdram->cr40, 0x00000000);
  79. out_be32(&sdram->cr41, 0x00C80064);
  80. out_be32(&sdram->cr42, 0x44520002);
  81. out_be32(&sdram->cr43, 0x00C80023);
  82. out_be32(&sdram->cr45, 0x0000C350);
  83. out_be32(&sdram->cr56, 0x04000000);
  84. out_be32(&sdram->cr57, 0x03000304);
  85. out_be32(&sdram->cr58, 0x40040000);
  86. out_be32(&sdram->cr59, 0xC0004004);
  87. out_be32(&sdram->cr60, 0x0642C000);
  88. out_be32(&sdram->cr61, 0x00000642);
  89. asm("tpf");
  90. out_be32(&sdram->cr09, 0x01000100);
  91. udelay(100);
  92. #endif
  93. gd->ram_size = dramsize;
  94. return 0;
  95. };
  96. int testdram(void)
  97. {
  98. return 0;
  99. }