ls1088a.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <i2c.h>
  8. #include <malloc.h>
  9. #include <errno.h>
  10. #include <netdev.h>
  11. #include <fsl_ifc.h>
  12. #include <fsl_ddr.h>
  13. #include <fsl_sec.h>
  14. #include <asm/io.h>
  15. #include <fdt_support.h>
  16. #include <linux/libfdt.h>
  17. #include <fsl-mc/fsl_mc.h>
  18. #include <env_internal.h>
  19. #include <asm/arch-fsl-layerscape/soc.h>
  20. #include <asm/arch/ppa.h>
  21. #include <hwconfig.h>
  22. #include <asm/arch/fsl_serdes.h>
  23. #include <asm/arch/soc.h>
  24. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  25. #include "../common/qixis.h"
  26. #include "ls1088a_qixis.h"
  27. #include "../common/vid.h"
  28. #include <fsl_immap.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #ifdef CONFIG_TARGET_LS1088AQDS
  31. #ifdef CONFIG_TFABOOT
  32. struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  33. {
  34. "nor0",
  35. CONFIG_SYS_NOR0_CSPR_EARLY,
  36. CONFIG_SYS_NOR0_CSPR_EXT,
  37. CONFIG_SYS_NOR_AMASK,
  38. CONFIG_SYS_NOR_CSOR,
  39. {
  40. CONFIG_SYS_NOR_FTIM0,
  41. CONFIG_SYS_NOR_FTIM1,
  42. CONFIG_SYS_NOR_FTIM2,
  43. CONFIG_SYS_NOR_FTIM3
  44. },
  45. 0,
  46. CONFIG_SYS_NOR0_CSPR,
  47. 0,
  48. },
  49. {
  50. "nor1",
  51. CONFIG_SYS_NOR1_CSPR_EARLY,
  52. CONFIG_SYS_NOR0_CSPR_EXT,
  53. CONFIG_SYS_NOR_AMASK_EARLY,
  54. CONFIG_SYS_NOR_CSOR,
  55. {
  56. CONFIG_SYS_NOR_FTIM0,
  57. CONFIG_SYS_NOR_FTIM1,
  58. CONFIG_SYS_NOR_FTIM2,
  59. CONFIG_SYS_NOR_FTIM3
  60. },
  61. 0,
  62. CONFIG_SYS_NOR1_CSPR,
  63. CONFIG_SYS_NOR_AMASK,
  64. },
  65. {
  66. "nand",
  67. CONFIG_SYS_NAND_CSPR,
  68. CONFIG_SYS_NAND_CSPR_EXT,
  69. CONFIG_SYS_NAND_AMASK,
  70. CONFIG_SYS_NAND_CSOR,
  71. {
  72. CONFIG_SYS_NAND_FTIM0,
  73. CONFIG_SYS_NAND_FTIM1,
  74. CONFIG_SYS_NAND_FTIM2,
  75. CONFIG_SYS_NAND_FTIM3
  76. },
  77. },
  78. {
  79. "fpga",
  80. CONFIG_SYS_FPGA_CSPR,
  81. CONFIG_SYS_FPGA_CSPR_EXT,
  82. SYS_FPGA_AMASK,
  83. CONFIG_SYS_FPGA_CSOR,
  84. {
  85. SYS_FPGA_CS_FTIM0,
  86. SYS_FPGA_CS_FTIM1,
  87. SYS_FPGA_CS_FTIM2,
  88. SYS_FPGA_CS_FTIM3
  89. },
  90. 0,
  91. SYS_FPGA_CSPR_FINAL,
  92. 0,
  93. }
  94. };
  95. struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  96. {
  97. "nand",
  98. CONFIG_SYS_NAND_CSPR,
  99. CONFIG_SYS_NAND_CSPR_EXT,
  100. CONFIG_SYS_NAND_AMASK,
  101. CONFIG_SYS_NAND_CSOR,
  102. {
  103. CONFIG_SYS_NAND_FTIM0,
  104. CONFIG_SYS_NAND_FTIM1,
  105. CONFIG_SYS_NAND_FTIM2,
  106. CONFIG_SYS_NAND_FTIM3
  107. },
  108. },
  109. {
  110. "reserved",
  111. },
  112. {
  113. "fpga",
  114. CONFIG_SYS_FPGA_CSPR,
  115. CONFIG_SYS_FPGA_CSPR_EXT,
  116. SYS_FPGA_AMASK,
  117. CONFIG_SYS_FPGA_CSOR,
  118. {
  119. SYS_FPGA_CS_FTIM0,
  120. SYS_FPGA_CS_FTIM1,
  121. SYS_FPGA_CS_FTIM2,
  122. SYS_FPGA_CS_FTIM3
  123. },
  124. 0,
  125. SYS_FPGA_CSPR_FINAL,
  126. 0,
  127. }
  128. };
  129. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  130. {
  131. enum boot_src src = get_boot_src();
  132. if (src == BOOT_SOURCE_QSPI_NOR)
  133. regs_info->regs = ifc_cfg_qspi_nor_boot;
  134. else
  135. regs_info->regs = ifc_cfg_ifc_nor_boot;
  136. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  137. }
  138. #endif /* CONFIG_TFABOOT */
  139. #endif /* CONFIG_TARGET_LS1088AQDS */
  140. int board_early_init_f(void)
  141. {
  142. #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
  143. i2c_early_init_f();
  144. #endif
  145. fsl_lsch3_early_init_f();
  146. return 0;
  147. }
  148. #ifdef CONFIG_FSL_QIXIS
  149. unsigned long long get_qixis_addr(void)
  150. {
  151. unsigned long long addr;
  152. if (gd->flags & GD_FLG_RELOC)
  153. addr = QIXIS_BASE_PHYS;
  154. else
  155. addr = QIXIS_BASE_PHYS_EARLY;
  156. /*
  157. * IFC address under 256MB is mapped to 0x30000000, any address above
  158. * is mapped to 0x5_10000000 up to 4GB.
  159. */
  160. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  161. return addr;
  162. }
  163. #endif
  164. #if defined(CONFIG_VID)
  165. int init_func_vid(void)
  166. {
  167. if (adjust_vdd(0) < 0)
  168. printf("core voltage not adjusted\n");
  169. return 0;
  170. }
  171. #endif
  172. int is_pb_board(void)
  173. {
  174. u8 board_id;
  175. board_id = QIXIS_READ(id);
  176. if (board_id == LS1088ARDB_PB_BOARD)
  177. return 1;
  178. else
  179. return 0;
  180. }
  181. int fixup_ls1088ardb_pb_banner(void *fdt)
  182. {
  183. fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
  184. return 0;
  185. }
  186. #if !defined(CONFIG_SPL_BUILD)
  187. int checkboard(void)
  188. {
  189. #ifdef CONFIG_TFABOOT
  190. enum boot_src src = get_boot_src();
  191. #endif
  192. char buf[64];
  193. u8 sw;
  194. static const char *const freq[] = {"100", "125", "156.25",
  195. "100 separate SSCG"};
  196. int clock;
  197. #ifdef CONFIG_TARGET_LS1088AQDS
  198. printf("Board: LS1088A-QDS, ");
  199. #else
  200. if (is_pb_board())
  201. printf("Board: LS1088ARDB-PB, ");
  202. else
  203. printf("Board: LS1088A-RDB, ");
  204. #endif
  205. sw = QIXIS_READ(arch);
  206. printf("Board Arch: V%d, ", sw >> 4);
  207. #ifdef CONFIG_TARGET_LS1088AQDS
  208. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  209. #else
  210. printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
  211. #endif
  212. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  213. sw = QIXIS_READ(brdcfg[0]);
  214. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  215. #ifdef CONFIG_TFABOOT
  216. if (src == BOOT_SOURCE_SD_MMC)
  217. puts("SD card\n");
  218. #else
  219. #ifdef CONFIG_SD_BOOT
  220. puts("SD card\n");
  221. #endif
  222. #endif /* CONFIG_TFABOOT */
  223. switch (sw) {
  224. #ifdef CONFIG_TARGET_LS1088AQDS
  225. case 0:
  226. case 1:
  227. case 2:
  228. case 3:
  229. case 4:
  230. case 5:
  231. case 6:
  232. case 7:
  233. printf("vBank: %d\n", sw);
  234. break;
  235. case 8:
  236. puts("PromJet\n");
  237. break;
  238. case 15:
  239. puts("IFCCard\n");
  240. break;
  241. case 14:
  242. #else
  243. case 0:
  244. #endif
  245. puts("QSPI:");
  246. sw = QIXIS_READ(brdcfg[0]);
  247. sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
  248. if (sw == 0 || sw == 4)
  249. puts("0\n");
  250. else if (sw == 1)
  251. puts("1\n");
  252. else
  253. puts("EMU\n");
  254. break;
  255. default:
  256. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  257. break;
  258. }
  259. #ifdef CONFIG_TARGET_LS1088AQDS
  260. printf("FPGA: v%d (%s), build %d",
  261. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  262. (int)qixis_read_minor());
  263. /* the timestamp string contains "\n" at the end */
  264. printf(" on %s", qixis_read_time(buf));
  265. #else
  266. printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  267. #endif
  268. /*
  269. * Display the actual SERDES reference clocks as configured by the
  270. * dip switches on the board. Note that the SWx registers could
  271. * technically be set to force the reference clocks to match the
  272. * values that the SERDES expects (or vice versa). For now, however,
  273. * we just display both values and hope the user notices when they
  274. * don't match.
  275. */
  276. puts("SERDES1 Reference : ");
  277. sw = QIXIS_READ(brdcfg[2]);
  278. clock = (sw >> 6) & 3;
  279. printf("Clock1 = %sMHz ", freq[clock]);
  280. clock = (sw >> 4) & 3;
  281. printf("Clock2 = %sMHz", freq[clock]);
  282. puts("\nSERDES2 Reference : ");
  283. clock = (sw >> 2) & 3;
  284. printf("Clock1 = %sMHz ", freq[clock]);
  285. clock = (sw >> 0) & 3;
  286. printf("Clock2 = %sMHz\n", freq[clock]);
  287. return 0;
  288. }
  289. #endif
  290. bool if_board_diff_clk(void)
  291. {
  292. #ifdef CONFIG_TARGET_LS1088AQDS
  293. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  294. return diff_conf & 0x40;
  295. #else
  296. u8 diff_conf = QIXIS_READ(dutcfg[11]);
  297. return diff_conf & 0x80;
  298. #endif
  299. }
  300. unsigned long get_board_sys_clk(void)
  301. {
  302. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  303. switch (sysclk_conf & 0x0f) {
  304. case QIXIS_SYSCLK_83:
  305. return 83333333;
  306. case QIXIS_SYSCLK_100:
  307. return 100000000;
  308. case QIXIS_SYSCLK_125:
  309. return 125000000;
  310. case QIXIS_SYSCLK_133:
  311. return 133333333;
  312. case QIXIS_SYSCLK_150:
  313. return 150000000;
  314. case QIXIS_SYSCLK_160:
  315. return 160000000;
  316. case QIXIS_SYSCLK_166:
  317. return 166666666;
  318. }
  319. return 66666666;
  320. }
  321. unsigned long get_board_ddr_clk(void)
  322. {
  323. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  324. if (if_board_diff_clk())
  325. return get_board_sys_clk();
  326. switch ((ddrclk_conf & 0x30) >> 4) {
  327. case QIXIS_DDRCLK_100:
  328. return 100000000;
  329. case QIXIS_DDRCLK_125:
  330. return 125000000;
  331. case QIXIS_DDRCLK_133:
  332. return 133333333;
  333. }
  334. return 66666666;
  335. }
  336. int select_i2c_ch_pca9547(u8 ch)
  337. {
  338. int ret;
  339. #ifndef CONFIG_DM_I2C
  340. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  341. #else
  342. struct udevice *dev;
  343. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  344. if (!ret)
  345. ret = dm_i2c_write(dev, 0, &ch, 1);
  346. #endif
  347. if (ret) {
  348. puts("PCA: failed to select proper channel\n");
  349. return ret;
  350. }
  351. return 0;
  352. }
  353. #if !defined(CONFIG_SPL_BUILD)
  354. void board_retimer_init(void)
  355. {
  356. u8 reg;
  357. /* Retimer is connected to I2C1_CH5 */
  358. select_i2c_ch_pca9547(I2C_MUX_CH5);
  359. /* Access to Control/Shared register */
  360. reg = 0x0;
  361. #ifndef CONFIG_DM_I2C
  362. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  363. #else
  364. struct udevice *dev;
  365. i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
  366. dm_i2c_write(dev, 0xff, &reg, 1);
  367. #endif
  368. /* Read device revision and ID */
  369. #ifndef CONFIG_DM_I2C
  370. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  371. #else
  372. dm_i2c_read(dev, 1, &reg, 1);
  373. #endif
  374. debug("Retimer version id = 0x%x\n", reg);
  375. /* Enable Broadcast. All writes target all channel register sets */
  376. reg = 0x0c;
  377. #ifndef CONFIG_DM_I2C
  378. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  379. #else
  380. dm_i2c_write(dev, 0xff, &reg, 1);
  381. #endif
  382. /* Reset Channel Registers */
  383. #ifndef CONFIG_DM_I2C
  384. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  385. #else
  386. dm_i2c_read(dev, 0, &reg, 1);
  387. #endif
  388. reg |= 0x4;
  389. #ifndef CONFIG_DM_I2C
  390. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  391. #else
  392. dm_i2c_write(dev, 0, &reg, 1);
  393. #endif
  394. /* Set data rate as 10.3125 Gbps */
  395. reg = 0x90;
  396. #ifndef CONFIG_DM_I2C
  397. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  398. #else
  399. dm_i2c_write(dev, 0x60, &reg, 1);
  400. #endif
  401. reg = 0xb3;
  402. #ifndef CONFIG_DM_I2C
  403. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  404. #else
  405. dm_i2c_write(dev, 0x61, &reg, 1);
  406. #endif
  407. reg = 0x90;
  408. #ifndef CONFIG_DM_I2C
  409. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  410. #else
  411. dm_i2c_write(dev, 0x62, &reg, 1);
  412. #endif
  413. reg = 0xb3;
  414. #ifndef CONFIG_DM_I2C
  415. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  416. #else
  417. dm_i2c_write(dev, 0x63, &reg, 1);
  418. #endif
  419. reg = 0xcd;
  420. #ifndef CONFIG_DM_I2C
  421. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  422. #else
  423. dm_i2c_write(dev, 0x64, &reg, 1);
  424. #endif
  425. /* Select VCO Divider to full rate (000) */
  426. #ifndef CONFIG_DM_I2C
  427. i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  428. #else
  429. dm_i2c_read(dev, 0x2F, &reg, 1);
  430. #endif
  431. reg &= 0x0f;
  432. reg |= 0x70;
  433. #ifndef CONFIG_DM_I2C
  434. i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
  435. #else
  436. dm_i2c_write(dev, 0x2F, &reg, 1);
  437. #endif
  438. #ifdef CONFIG_TARGET_LS1088AQDS
  439. /* Retimer is connected to I2C1_CH5 */
  440. select_i2c_ch_pca9547(I2C_MUX_CH5);
  441. /* Access to Control/Shared register */
  442. reg = 0x0;
  443. #ifndef CONFIG_DM_I2C
  444. i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  445. #else
  446. i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
  447. dm_i2c_write(dev, 0xff, &reg, 1);
  448. #endif
  449. /* Read device revision and ID */
  450. #ifndef CONFIG_DM_I2C
  451. i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
  452. #else
  453. dm_i2c_read(dev, 1, &reg, 1);
  454. #endif
  455. debug("Retimer version id = 0x%x\n", reg);
  456. /* Enable Broadcast. All writes target all channel register sets */
  457. reg = 0x0c;
  458. #ifndef CONFIG_DM_I2C
  459. i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
  460. #else
  461. dm_i2c_write(dev, 0xff, &reg, 1);
  462. #endif
  463. /* Reset Channel Registers */
  464. #ifndef CONFIG_DM_I2C
  465. i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  466. #else
  467. dm_i2c_read(dev, 0, &reg, 1);
  468. #endif
  469. reg |= 0x4;
  470. #ifndef CONFIG_DM_I2C
  471. i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
  472. #else
  473. dm_i2c_write(dev, 0, &reg, 1);
  474. #endif
  475. /* Set data rate as 10.3125 Gbps */
  476. reg = 0x90;
  477. #ifndef CONFIG_DM_I2C
  478. i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
  479. #else
  480. dm_i2c_write(dev, 0x60, &reg, 1);
  481. #endif
  482. reg = 0xb3;
  483. #ifndef CONFIG_DM_I2C
  484. i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
  485. #else
  486. dm_i2c_write(dev, 0x61, &reg, 1);
  487. #endif
  488. reg = 0x90;
  489. #ifndef CONFIG_DM_I2C
  490. i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
  491. #else
  492. dm_i2c_write(dev, 0x62, &reg, 1);
  493. #endif
  494. reg = 0xb3;
  495. #ifndef CONFIG_DM_I2C
  496. i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
  497. #else
  498. dm_i2c_write(dev, 0x63, &reg, 1);
  499. #endif
  500. reg = 0xcd;
  501. #ifndef CONFIG_DM_I2C
  502. i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
  503. #else
  504. dm_i2c_write(dev, 0x64, &reg, 1);
  505. #endif
  506. /* Select VCO Divider to full rate (000) */
  507. #ifndef CONFIG_DM_I2C
  508. i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  509. #else
  510. dm_i2c_read(dev, 0x2F, &reg, 1);
  511. #endif
  512. reg &= 0x0f;
  513. reg |= 0x70;
  514. #ifndef CONFIG_DM_I2C
  515. i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
  516. #else
  517. dm_i2c_write(dev, 0x2F, &reg, 1);
  518. #endif
  519. #endif
  520. /*return the default channel*/
  521. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  522. }
  523. #ifdef CONFIG_MISC_INIT_R
  524. int misc_init_r(void)
  525. {
  526. #ifdef CONFIG_TARGET_LS1088ARDB
  527. u8 brdcfg5;
  528. if (hwconfig("esdhc-force-sd")) {
  529. brdcfg5 = QIXIS_READ(brdcfg[5]);
  530. brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
  531. brdcfg5 |= BRDCFG5_FORCE_SD;
  532. QIXIS_WRITE(brdcfg[5], brdcfg5);
  533. }
  534. #endif
  535. #ifdef CONFIG_TARGET_LS1088AQDS
  536. u8 brdcfg4, brdcfg5;
  537. if (hwconfig("dspi-on-board")) {
  538. brdcfg4 = QIXIS_READ(brdcfg[4]);
  539. brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
  540. brdcfg4 |= BRDCFG4_SPI;
  541. QIXIS_WRITE(brdcfg[4], brdcfg4);
  542. brdcfg5 = QIXIS_READ(brdcfg[5]);
  543. brdcfg5 &= ~BRDCFG5_SPR_MASK;
  544. brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
  545. QIXIS_WRITE(brdcfg[5], brdcfg5);
  546. } else if (hwconfig("dspi-off-board")) {
  547. brdcfg4 = QIXIS_READ(brdcfg[4]);
  548. brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
  549. brdcfg4 |= BRDCFG4_SPI;
  550. QIXIS_WRITE(brdcfg[4], brdcfg4);
  551. brdcfg5 = QIXIS_READ(brdcfg[5]);
  552. brdcfg5 &= ~BRDCFG5_SPR_MASK;
  553. brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
  554. QIXIS_WRITE(brdcfg[5], brdcfg5);
  555. }
  556. #endif
  557. return 0;
  558. }
  559. #endif
  560. #endif
  561. int i2c_multiplexer_select_vid_channel(u8 channel)
  562. {
  563. return select_i2c_ch_pca9547(channel);
  564. }
  565. #ifdef CONFIG_TARGET_LS1088AQDS
  566. /* read the current value(SVDD) of the LTM Regulator Voltage */
  567. int get_serdes_volt(void)
  568. {
  569. int ret, vcode = 0;
  570. u8 chan = PWM_CHANNEL0;
  571. /* Select the PAGE 0 using PMBus commands PAGE for VDD */
  572. #ifndef CONFIG_DM_I2C
  573. ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
  574. PMBUS_CMD_PAGE, 1, &chan, 1);
  575. #else
  576. struct udevice *dev;
  577. ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
  578. if (!ret)
  579. ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
  580. &chan, 1);
  581. #endif
  582. if (ret) {
  583. printf("VID: failed to select VDD Page 0\n");
  584. return ret;
  585. }
  586. /* Read the output voltage using PMBus command READ_VOUT */
  587. #ifndef CONFIG_DM_I2C
  588. ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
  589. PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
  590. #else
  591. dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
  592. #endif
  593. if (ret) {
  594. printf("VID: failed to read the volatge\n");
  595. return ret;
  596. }
  597. return vcode;
  598. }
  599. int set_serdes_volt(int svdd)
  600. {
  601. int ret, vdd_last;
  602. u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
  603. svdd & 0xFF, (svdd & 0xFF00) >> 8};
  604. /* Write the desired voltage code to the SVDD regulator */
  605. #ifndef CONFIG_DM_I2C
  606. ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
  607. PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
  608. #else
  609. struct udevice *dev;
  610. ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
  611. if (!ret)
  612. ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
  613. (void *)&buff, 5);
  614. #endif
  615. if (ret) {
  616. printf("VID: I2C failed to write to the volatge regulator\n");
  617. return -1;
  618. }
  619. /* Wait for the volatge to get to the desired value */
  620. do {
  621. vdd_last = get_serdes_volt();
  622. if (vdd_last < 0) {
  623. printf("VID: Couldn't read sensor abort VID adjust\n");
  624. return -1;
  625. }
  626. } while (vdd_last != svdd);
  627. return 1;
  628. }
  629. #else
  630. int get_serdes_volt(void)
  631. {
  632. return 0;
  633. }
  634. int set_serdes_volt(int svdd)
  635. {
  636. int ret;
  637. u8 brdcfg4;
  638. printf("SVDD changing of RDB\n");
  639. /* Read the BRDCFG54 via CLPD */
  640. #ifndef CONFIG_DM_I2C
  641. ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
  642. QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
  643. #else
  644. struct udevice *dev;
  645. ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
  646. if (!ret)
  647. ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
  648. (void *)&brdcfg4, 1);
  649. #endif
  650. if (ret) {
  651. printf("VID: I2C failed to read the CPLD BRDCFG4\n");
  652. return -1;
  653. }
  654. brdcfg4 = brdcfg4 | 0x08;
  655. /* Write to the BRDCFG4 */
  656. #ifndef CONFIG_DM_I2C
  657. ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
  658. QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
  659. #else
  660. ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
  661. (void *)&brdcfg4, 1);
  662. #endif
  663. if (ret) {
  664. debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
  665. return -1;
  666. }
  667. /* Wait for the volatge to get to the desired value */
  668. udelay(10000);
  669. return 1;
  670. }
  671. #endif
  672. /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
  673. int board_adjust_vdd(int vdd)
  674. {
  675. int ret = 0;
  676. debug("%s: vdd = %d\n", __func__, vdd);
  677. /* Special settings to be performed when voltage is 900mV */
  678. if (vdd == 900) {
  679. ret = setup_serdes_volt(vdd);
  680. if (ret < 0) {
  681. ret = -1;
  682. goto exit;
  683. }
  684. }
  685. exit:
  686. return ret;
  687. }
  688. #if !defined(CONFIG_SPL_BUILD)
  689. int board_init(void)
  690. {
  691. init_final_memctl_regs();
  692. #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  693. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  694. #endif
  695. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  696. board_retimer_init();
  697. #ifdef CONFIG_ENV_IS_NOWHERE
  698. gd->env_addr = (ulong)&default_environment[0];
  699. #endif
  700. #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
  701. /* invert AQR105 IRQ pins polarity */
  702. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
  703. #endif
  704. #ifdef CONFIG_FSL_CAAM
  705. sec_init();
  706. #endif
  707. #ifdef CONFIG_FSL_LS_PPA
  708. ppa_init();
  709. #endif
  710. return 0;
  711. }
  712. void detail_board_ddr_info(void)
  713. {
  714. puts("\nDDR ");
  715. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  716. print_ddr_info(0);
  717. }
  718. #if defined(CONFIG_ARCH_MISC_INIT)
  719. int arch_misc_init(void)
  720. {
  721. return 0;
  722. }
  723. #endif
  724. #ifdef CONFIG_FSL_MC_ENET
  725. void board_quiesce_devices(void)
  726. {
  727. fsl_mc_ldpaa_exit(gd->bd);
  728. }
  729. void fdt_fixup_board_enet(void *fdt)
  730. {
  731. int offset;
  732. offset = fdt_path_offset(fdt, "/fsl-mc");
  733. if (offset < 0)
  734. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  735. if (offset < 0) {
  736. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  737. __func__, offset);
  738. return;
  739. }
  740. if (get_mc_boot_status() == 0 &&
  741. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  742. fdt_status_okay(fdt, offset);
  743. else
  744. fdt_status_fail(fdt, offset);
  745. }
  746. #endif
  747. #ifdef CONFIG_OF_BOARD_SETUP
  748. void fsl_fdt_fixup_flash(void *fdt)
  749. {
  750. int offset;
  751. #ifdef CONFIG_TFABOOT
  752. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  753. u32 val;
  754. #endif
  755. /*
  756. * IFC-NOR and QSPI are muxed on SoC.
  757. * So disable IFC node in dts if QSPI is enabled or
  758. * disable QSPI node in dts in case QSPI is not enabled.
  759. */
  760. #ifdef CONFIG_TFABOOT
  761. enum boot_src src = get_boot_src();
  762. bool disable_ifc = false;
  763. switch (src) {
  764. case BOOT_SOURCE_IFC_NOR:
  765. disable_ifc = false;
  766. break;
  767. case BOOT_SOURCE_QSPI_NOR:
  768. disable_ifc = true;
  769. break;
  770. default:
  771. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  772. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  773. disable_ifc = true;
  774. break;
  775. }
  776. if (disable_ifc) {
  777. offset = fdt_path_offset(fdt, "/soc/ifc/nor");
  778. if (offset < 0)
  779. offset = fdt_path_offset(fdt, "/ifc/nor");
  780. } else {
  781. offset = fdt_path_offset(fdt, "/soc/quadspi");
  782. if (offset < 0)
  783. offset = fdt_path_offset(fdt, "/quadspi");
  784. }
  785. #else
  786. #ifdef CONFIG_FSL_QSPI
  787. offset = fdt_path_offset(fdt, "/soc/ifc/nor");
  788. if (offset < 0)
  789. offset = fdt_path_offset(fdt, "/ifc/nor");
  790. #else
  791. offset = fdt_path_offset(fdt, "/soc/quadspi");
  792. if (offset < 0)
  793. offset = fdt_path_offset(fdt, "/quadspi");
  794. #endif
  795. #endif
  796. if (offset < 0)
  797. return;
  798. fdt_status_disabled(fdt, offset);
  799. }
  800. int ft_board_setup(void *blob, bd_t *bd)
  801. {
  802. int i;
  803. u16 mc_memory_bank = 0;
  804. u64 *base;
  805. u64 *size;
  806. u64 mc_memory_base = 0;
  807. u64 mc_memory_size = 0;
  808. u16 total_memory_banks;
  809. ft_cpu_setup(blob, bd);
  810. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  811. if (mc_memory_base != 0)
  812. mc_memory_bank++;
  813. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  814. base = calloc(total_memory_banks, sizeof(u64));
  815. size = calloc(total_memory_banks, sizeof(u64));
  816. /* fixup DT for the two GPP DDR banks */
  817. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  818. base[i] = gd->bd->bi_dram[i].start;
  819. size[i] = gd->bd->bi_dram[i].size;
  820. }
  821. #ifdef CONFIG_RESV_RAM
  822. /* reduce size if reserved memory is within this bank */
  823. if (gd->arch.resv_ram >= base[0] &&
  824. gd->arch.resv_ram < base[0] + size[0])
  825. size[0] = gd->arch.resv_ram - base[0];
  826. else if (gd->arch.resv_ram >= base[1] &&
  827. gd->arch.resv_ram < base[1] + size[1])
  828. size[1] = gd->arch.resv_ram - base[1];
  829. #endif
  830. if (mc_memory_base != 0) {
  831. for (i = 0; i <= total_memory_banks; i++) {
  832. if (base[i] == 0 && size[i] == 0) {
  833. base[i] = mc_memory_base;
  834. size[i] = mc_memory_size;
  835. break;
  836. }
  837. }
  838. }
  839. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  840. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  841. fsl_fdt_fixup_flash(blob);
  842. #ifdef CONFIG_FSL_MC_ENET
  843. fdt_fixup_board_enet(blob);
  844. #endif
  845. fdt_fixup_icid(blob);
  846. if (is_pb_board())
  847. fixup_ls1088ardb_pb_banner(blob);
  848. return 0;
  849. }
  850. #endif
  851. #endif /* defined(CONFIG_SPL_BUILD) */
  852. #ifdef CONFIG_TFABOOT
  853. #ifdef CONFIG_MTD_NOR_FLASH
  854. int is_flash_available(void)
  855. {
  856. char *env_hwconfig = env_get("hwconfig");
  857. enum boot_src src = get_boot_src();
  858. int is_nor_flash_available = 1;
  859. switch (src) {
  860. case BOOT_SOURCE_IFC_NOR:
  861. is_nor_flash_available = 1;
  862. break;
  863. case BOOT_SOURCE_QSPI_NOR:
  864. is_nor_flash_available = 0;
  865. break;
  866. /*
  867. * In Case of SD boot,if qspi is defined in env_hwconfig
  868. * disable nor flash probe.
  869. */
  870. default:
  871. if (hwconfig_f("qspi", env_hwconfig))
  872. is_nor_flash_available = 0;
  873. break;
  874. }
  875. return is_nor_flash_available;
  876. }
  877. #endif
  878. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  879. void *env_sf_get_env_addr(void)
  880. {
  881. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  882. }
  883. #endif
  884. #endif