eth_ls1088aqds.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <netdev.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <hwconfig.h>
  12. #include <fsl_mdio.h>
  13. #include <malloc.h>
  14. #include <phy.h>
  15. #include <fm_eth.h>
  16. #include <i2c.h>
  17. #include <miiphy.h>
  18. #include <fsl-mc/fsl_mc.h>
  19. #include <fsl-mc/ldpaa_wriop.h>
  20. #include "../common/qixis.h"
  21. #include "ls1088a_qixis.h"
  22. #ifdef CONFIG_FSL_MC_ENET
  23. #define SFP_TX 0
  24. /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  25. * Bank 1 -> Lanes A, B, C, D,
  26. * Bank 2 -> Lanes A,B, C, D,
  27. */
  28. /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
  29. * means that the mapping must be determined dynamically, or that the lane
  30. * maps to something other than a board slot.
  31. */
  32. static u8 lane_to_slot_fsm1[] = {
  33. 0, 0, 0, 0, 0, 0, 0, 0
  34. };
  35. /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  36. * housed.
  37. */
  38. static int xqsgii_riser_phy_addr[] = {
  39. XQSGMII_CARD_PHY1_PORT0_ADDR,
  40. XQSGMII_CARD_PHY2_PORT0_ADDR,
  41. XQSGMII_CARD_PHY3_PORT0_ADDR,
  42. XQSGMII_CARD_PHY4_PORT0_ADDR,
  43. XQSGMII_CARD_PHY3_PORT2_ADDR,
  44. XQSGMII_CARD_PHY1_PORT2_ADDR,
  45. XQSGMII_CARD_PHY4_PORT2_ADDR,
  46. XQSGMII_CARD_PHY2_PORT2_ADDR,
  47. };
  48. static int sgmii_riser_phy_addr[] = {
  49. SGMII_CARD_PORT1_PHY_ADDR,
  50. SGMII_CARD_PORT2_PHY_ADDR,
  51. SGMII_CARD_PORT3_PHY_ADDR,
  52. SGMII_CARD_PORT4_PHY_ADDR,
  53. };
  54. /* Slot2 does not have EMI connections */
  55. #define EMI_NONE 0xFF
  56. #define EMI1_RGMII1 0
  57. #define EMI1_RGMII2 1
  58. #define EMI1_SLOT1 2
  59. static const char * const mdio_names[] = {
  60. "LS1088A_QDS_MDIO0",
  61. "LS1088A_QDS_MDIO1",
  62. "LS1088A_QDS_MDIO2",
  63. DEFAULT_WRIOP_MDIO2_NAME,
  64. };
  65. struct ls1088a_qds_mdio {
  66. u8 muxval;
  67. struct mii_dev *realbus;
  68. };
  69. struct reg_pair {
  70. uint addr;
  71. u8 *val;
  72. };
  73. static void sgmii_configure_repeater(int dpmac)
  74. {
  75. struct mii_dev *bus;
  76. uint8_t a = 0xf;
  77. int i, j, k, ret;
  78. unsigned short value;
  79. const char *dev = "LS1088A_QDS_MDIO2";
  80. int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  81. int i2c_phy_addr = 0;
  82. int phy_addr = 0;
  83. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  84. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  85. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  86. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  87. u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
  88. struct reg_pair reg_pair[10] = {
  89. {6, &reg_val[0]}, {4, &reg_val[1]},
  90. {8, &reg_val[2]}, {0xf, NULL},
  91. {0x11, NULL}, {0x16, NULL},
  92. {0x18, NULL}, {0x23, &reg_val[3]},
  93. {0x2d, &reg_val[4]}, {4, &reg_val[5]},
  94. };
  95. #ifdef CONFIG_DM_I2C
  96. struct udevice *udev;
  97. #endif
  98. /* Set I2c to Slot 1 */
  99. #ifndef CONFIG_DM_I2C
  100. ret = i2c_write(0x77, 0, 0, &a, 1);
  101. #else
  102. ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
  103. if (!ret)
  104. ret = dm_i2c_write(udev, 0, &a, 1);
  105. #endif
  106. if (ret)
  107. goto error;
  108. switch (dpmac) {
  109. case 1:
  110. i2c_phy_addr = i2c_addr[1];
  111. phy_addr = 4;
  112. break;
  113. case 2:
  114. i2c_phy_addr = i2c_addr[0];
  115. phy_addr = 0;
  116. break;
  117. case 3:
  118. i2c_phy_addr = i2c_addr[3];
  119. phy_addr = 0xc;
  120. break;
  121. case 7:
  122. i2c_phy_addr = i2c_addr[2];
  123. phy_addr = 8;
  124. break;
  125. }
  126. /* Check the PHY status */
  127. ret = miiphy_set_current_dev(dev);
  128. if (ret > 0)
  129. goto error;
  130. bus = mdio_get_current_dev();
  131. debug("Reading from bus %s\n", bus->name);
  132. ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  133. if (ret > 0)
  134. goto error;
  135. mdelay(10);
  136. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  137. if (ret > 0)
  138. goto error;
  139. mdelay(10);
  140. if ((value & 0xfff) == 0x401) {
  141. miiphy_write(dev, phy_addr, 0x1f, 0);
  142. printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
  143. return;
  144. }
  145. #ifdef CONFIG_DM_I2C
  146. i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
  147. #endif
  148. for (i = 0; i < 4; i++) {
  149. for (j = 0; j < 4; j++) {
  150. reg_pair[3].val = &ch_a_eq[i];
  151. reg_pair[4].val = &ch_a_ctl2[j];
  152. reg_pair[5].val = &ch_b_eq[i];
  153. reg_pair[6].val = &ch_b_ctl2[j];
  154. for (k = 0; k < 10; k++) {
  155. #ifndef CONFIG_DM_I2C
  156. ret = i2c_write(i2c_phy_addr,
  157. reg_pair[k].addr,
  158. 1, reg_pair[k].val, 1);
  159. #else
  160. ret = i2c_get_chip_for_busnum(0,
  161. i2c_phy_addr,
  162. 1, &udev);
  163. if (!ret)
  164. ret = dm_i2c_write(udev,
  165. reg_pair[k].addr,
  166. reg_pair[k].val, 1);
  167. #endif
  168. if (ret)
  169. goto error;
  170. }
  171. mdelay(100);
  172. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  173. if (ret > 0)
  174. goto error;
  175. mdelay(100);
  176. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  177. if (ret > 0)
  178. goto error;
  179. if ((value & 0xfff) == 0x401) {
  180. printf("DPMAC %d :PHY is configured ",
  181. dpmac);
  182. printf("after setting repeater 0x%x\n",
  183. value);
  184. i = 5;
  185. j = 5;
  186. } else {
  187. printf("DPMAC %d :PHY is failed to ",
  188. dpmac);
  189. printf("configure the repeater 0x%x\n", value);
  190. }
  191. }
  192. }
  193. miiphy_write(dev, phy_addr, 0x1f, 0);
  194. error:
  195. if (ret)
  196. printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
  197. return;
  198. }
  199. static void qsgmii_configure_repeater(int dpmac)
  200. {
  201. uint8_t a = 0xf;
  202. int i, j, k;
  203. int i2c_phy_addr = 0;
  204. int phy_addr = 0;
  205. int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  206. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  207. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  208. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  209. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  210. u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
  211. struct reg_pair reg_pair[10] = {
  212. {6, &reg_val[0]}, {4, &reg_val[1]},
  213. {8, &reg_val[2]}, {0xf, NULL},
  214. {0x11, NULL}, {0x16, NULL},
  215. {0x18, NULL}, {0x23, &reg_val[3]},
  216. {0x2d, &reg_val[4]}, {4, &reg_val[5]},
  217. };
  218. const char *dev = mdio_names[EMI1_SLOT1];
  219. int ret = 0;
  220. unsigned short value;
  221. #ifdef CONFIG_DM_I2C
  222. struct udevice *udev;
  223. #endif
  224. /* Set I2c to Slot 1 */
  225. #ifndef CONFIG_DM_I2C
  226. ret = i2c_write(0x77, 0, 0, &a, 1);
  227. #else
  228. ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
  229. if (!ret)
  230. ret = dm_i2c_write(udev, 0, &a, 1);
  231. #endif
  232. if (ret)
  233. goto error;
  234. switch (dpmac) {
  235. case 7:
  236. case 8:
  237. case 9:
  238. case 10:
  239. i2c_phy_addr = i2c_addr[2];
  240. phy_addr = 8;
  241. break;
  242. case 3:
  243. case 4:
  244. case 5:
  245. case 6:
  246. i2c_phy_addr = i2c_addr[3];
  247. phy_addr = 0xc;
  248. break;
  249. }
  250. /* Check the PHY status */
  251. ret = miiphy_set_current_dev(dev);
  252. ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  253. mdelay(10);
  254. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  255. mdelay(10);
  256. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  257. mdelay(10);
  258. if ((value & 0xf) == 0xf) {
  259. miiphy_write(dev, phy_addr, 0x1f, 0);
  260. printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
  261. return;
  262. }
  263. #ifdef CONFIG_DM_I2C
  264. i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
  265. #endif
  266. for (i = 0; i < 4; i++) {
  267. for (j = 0; j < 4; j++) {
  268. reg_pair[3].val = &ch_a_eq[i];
  269. reg_pair[4].val = &ch_a_ctl2[j];
  270. reg_pair[5].val = &ch_b_eq[i];
  271. reg_pair[6].val = &ch_b_ctl2[j];
  272. for (k = 0; k < 10; k++) {
  273. #ifndef CONFIG_DM_I2C
  274. ret = i2c_write(i2c_phy_addr,
  275. reg_pair[k].addr,
  276. 1, reg_pair[k].val, 1);
  277. #else
  278. ret = i2c_get_chip_for_busnum(0,
  279. i2c_addr[dpmac],
  280. 1, &udev);
  281. if (!ret)
  282. ret = dm_i2c_write(udev,
  283. reg_pair[k].addr,
  284. reg_pair[k].val, 1);
  285. #endif
  286. if (ret)
  287. goto error;
  288. }
  289. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  290. if (ret > 0)
  291. goto error;
  292. mdelay(1);
  293. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  294. if (ret > 0)
  295. goto error;
  296. mdelay(10);
  297. if ((value & 0xf) == 0xf) {
  298. miiphy_write(dev, phy_addr, 0x1f, 0);
  299. printf("DPMAC %d :PHY is ..... Configured\n",
  300. dpmac);
  301. return;
  302. }
  303. }
  304. }
  305. error:
  306. printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
  307. return;
  308. }
  309. static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
  310. {
  311. return mdio_names[muxval];
  312. }
  313. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  314. {
  315. struct mii_dev *bus;
  316. const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
  317. if (!name) {
  318. printf("No bus for muxval %x\n", muxval);
  319. return NULL;
  320. }
  321. bus = miiphy_get_dev_by_name(name);
  322. if (!bus) {
  323. printf("No bus by name %s\n", name);
  324. return NULL;
  325. }
  326. return bus;
  327. }
  328. static void ls1088a_qds_enable_SFP_TX(u8 muxval)
  329. {
  330. u8 brdcfg9;
  331. brdcfg9 = QIXIS_READ(brdcfg[9]);
  332. brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
  333. brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
  334. QIXIS_WRITE(brdcfg[9], brdcfg9);
  335. }
  336. static void ls1088a_qds_mux_mdio(u8 muxval)
  337. {
  338. u8 brdcfg4;
  339. if (muxval <= 5) {
  340. brdcfg4 = QIXIS_READ(brdcfg[4]);
  341. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  342. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  343. QIXIS_WRITE(brdcfg[4], brdcfg4);
  344. }
  345. }
  346. static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
  347. int devad, int regnum)
  348. {
  349. struct ls1088a_qds_mdio *priv = bus->priv;
  350. ls1088a_qds_mux_mdio(priv->muxval);
  351. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  352. }
  353. static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  354. int regnum, u16 value)
  355. {
  356. struct ls1088a_qds_mdio *priv = bus->priv;
  357. ls1088a_qds_mux_mdio(priv->muxval);
  358. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  359. }
  360. static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
  361. {
  362. struct ls1088a_qds_mdio *priv = bus->priv;
  363. return priv->realbus->reset(priv->realbus);
  364. }
  365. static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
  366. {
  367. struct ls1088a_qds_mdio *pmdio;
  368. struct mii_dev *bus = mdio_alloc();
  369. if (!bus) {
  370. printf("Failed to allocate ls1088a_qds MDIO bus\n");
  371. return -1;
  372. }
  373. pmdio = malloc(sizeof(*pmdio));
  374. if (!pmdio) {
  375. printf("Failed to allocate ls1088a_qds private data\n");
  376. free(bus);
  377. return -1;
  378. }
  379. bus->read = ls1088a_qds_mdio_read;
  380. bus->write = ls1088a_qds_mdio_write;
  381. bus->reset = ls1088a_qds_mdio_reset;
  382. sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
  383. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  384. if (!pmdio->realbus) {
  385. printf("No bus with name %s\n", realbusname);
  386. free(bus);
  387. free(pmdio);
  388. return -1;
  389. }
  390. pmdio->muxval = muxval;
  391. bus->priv = pmdio;
  392. return mdio_register(bus);
  393. }
  394. /*
  395. * Initialize the dpmac_info array.
  396. *
  397. */
  398. static void initialize_dpmac_to_slot(void)
  399. {
  400. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  401. u32 serdes1_prtcl, cfg;
  402. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  403. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  404. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  405. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  406. switch (serdes1_prtcl) {
  407. case 0x12:
  408. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  409. serdes1_prtcl);
  410. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  411. lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  412. lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  413. lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
  414. break;
  415. case 0x15:
  416. case 0x1D:
  417. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  418. serdes1_prtcl);
  419. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  420. lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  421. lane_to_slot_fsm1[2] = EMI_NONE;
  422. lane_to_slot_fsm1[3] = EMI_NONE;
  423. break;
  424. case 0x1E:
  425. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  426. serdes1_prtcl);
  427. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  428. lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
  429. lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  430. lane_to_slot_fsm1[3] = EMI_NONE;
  431. break;
  432. case 0x3A:
  433. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  434. serdes1_prtcl);
  435. lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
  436. lane_to_slot_fsm1[1] = EMI_NONE;
  437. lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
  438. lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
  439. break;
  440. default:
  441. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  442. __func__, serdes1_prtcl);
  443. break;
  444. }
  445. }
  446. void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
  447. {
  448. struct mii_dev *bus;
  449. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  450. u32 serdes1_prtcl, cfg;
  451. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  452. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  453. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  454. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  455. int *riser_phy_addr;
  456. char *env_hwconfig = env_get("hwconfig");
  457. if (hwconfig_f("xqsgmii", env_hwconfig))
  458. riser_phy_addr = &xqsgii_riser_phy_addr[0];
  459. else
  460. riser_phy_addr = &sgmii_riser_phy_addr[0];
  461. switch (serdes1_prtcl) {
  462. case 0x12:
  463. case 0x15:
  464. case 0x1E:
  465. case 0x3A:
  466. switch (dpmac_id) {
  467. case 1:
  468. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
  469. break;
  470. case 2:
  471. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
  472. break;
  473. case 3:
  474. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
  475. break;
  476. case 7:
  477. wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
  478. break;
  479. default:
  480. printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
  481. break;
  482. }
  483. break;
  484. default:
  485. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  486. __func__, serdes1_prtcl);
  487. return;
  488. }
  489. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  490. bus = mii_dev_for_muxval(EMI1_SLOT1);
  491. wriop_set_mdio(dpmac_id, bus);
  492. }
  493. void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
  494. {
  495. struct mii_dev *bus;
  496. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  497. u32 serdes1_prtcl, cfg;
  498. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  499. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  500. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  501. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  502. switch (serdes1_prtcl) {
  503. case 0x1D:
  504. case 0x1E:
  505. switch (dpmac_id) {
  506. case 3:
  507. case 4:
  508. case 5:
  509. case 6:
  510. wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
  511. break;
  512. case 7:
  513. case 8:
  514. case 9:
  515. case 10:
  516. wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
  517. break;
  518. }
  519. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  520. bus = mii_dev_for_muxval(EMI1_SLOT1);
  521. wriop_set_mdio(dpmac_id, bus);
  522. break;
  523. default:
  524. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  525. serdes1_prtcl);
  526. break;
  527. }
  528. }
  529. void ls1088a_handle_phy_interface_xsgmii(int i)
  530. {
  531. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  532. u32 serdes1_prtcl, cfg;
  533. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  534. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  535. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  536. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  537. switch (serdes1_prtcl) {
  538. case 0x15:
  539. case 0x1D:
  540. case 0x1E:
  541. wriop_set_phy_address(i, 0, i + 26);
  542. ls1088a_qds_enable_SFP_TX(SFP_TX);
  543. break;
  544. default:
  545. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  546. serdes1_prtcl);
  547. break;
  548. }
  549. }
  550. static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
  551. {
  552. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  553. u32 serdes1_prtcl, cfg;
  554. struct mii_dev *bus;
  555. cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
  556. FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  557. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  558. serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
  559. switch (dpmac_id) {
  560. case 4:
  561. wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
  562. dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
  563. bus = mii_dev_for_muxval(EMI1_RGMII1);
  564. wriop_set_mdio(dpmac_id, bus);
  565. break;
  566. case 5:
  567. wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
  568. dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
  569. bus = mii_dev_for_muxval(EMI1_RGMII2);
  570. wriop_set_mdio(dpmac_id, bus);
  571. break;
  572. default:
  573. printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
  574. serdes1_prtcl);
  575. break;
  576. }
  577. }
  578. #endif
  579. int board_eth_init(bd_t *bis)
  580. {
  581. int error = 0, i;
  582. #ifdef CONFIG_FSL_MC_ENET
  583. struct memac_mdio_info *memac_mdio0_info;
  584. char *env_hwconfig = env_get("hwconfig");
  585. initialize_dpmac_to_slot();
  586. memac_mdio0_info = (struct memac_mdio_info *)malloc(
  587. sizeof(struct memac_mdio_info));
  588. memac_mdio0_info->regs =
  589. (struct memac_mdio_controller *)
  590. CONFIG_SYS_FSL_WRIOP1_MDIO1;
  591. memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
  592. /* Register the real MDIO1 bus */
  593. fm_memac_mdio_init(bis, memac_mdio0_info);
  594. /* Register the muxing front-ends to the MDIO buses */
  595. ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
  596. ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
  597. ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
  598. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  599. switch (wriop_get_enet_if(i)) {
  600. case PHY_INTERFACE_MODE_RGMII:
  601. case PHY_INTERFACE_MODE_RGMII_ID:
  602. ls1088a_handle_phy_interface_rgmii(i);
  603. break;
  604. case PHY_INTERFACE_MODE_QSGMII:
  605. ls1088a_handle_phy_interface_qsgmii(i);
  606. break;
  607. case PHY_INTERFACE_MODE_SGMII:
  608. ls1088a_handle_phy_interface_sgmii(i);
  609. break;
  610. case PHY_INTERFACE_MODE_XGMII:
  611. ls1088a_handle_phy_interface_xsgmii(i);
  612. break;
  613. default:
  614. break;
  615. if (i == 16)
  616. i = NUM_WRIOP_PORTS;
  617. }
  618. }
  619. error = cpu_eth_init(bis);
  620. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  621. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  622. switch (wriop_get_enet_if(i)) {
  623. case PHY_INTERFACE_MODE_QSGMII:
  624. qsgmii_configure_repeater(i);
  625. break;
  626. case PHY_INTERFACE_MODE_SGMII:
  627. sgmii_configure_repeater(i);
  628. break;
  629. default:
  630. break;
  631. }
  632. if (i == 16)
  633. i = NUM_WRIOP_PORTS;
  634. }
  635. }
  636. #endif
  637. error = pci_eth_init(bis);
  638. return error;
  639. }
  640. #if defined(CONFIG_RESET_PHY_R)
  641. void reset_phy(void)
  642. {
  643. mc_env_boot();
  644. }
  645. #endif /* CONFIG_RESET_PHY_R */