ddr.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include "ddr.h"
  9. #ifdef CONFIG_FSL_DEEP_SLEEP
  10. #include <fsl_sleep.h>
  11. #endif
  12. #include <asm/arch/clock.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. void fsl_ddr_board_options(memctl_options_t *popts,
  15. dimm_params_t *pdimm,
  16. unsigned int ctrl_num)
  17. {
  18. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  19. ulong ddr_freq;
  20. if (ctrl_num > 1) {
  21. printf("Not supported controller number %d\n", ctrl_num);
  22. return;
  23. }
  24. if (!pdimm->n_ranks)
  25. return;
  26. if (popts->registered_dimm_en)
  27. pbsp = rdimms[0];
  28. else
  29. pbsp = udimms[0];
  30. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  31. * freqency and n_banks specified in board_specific_parameters table.
  32. */
  33. ddr_freq = get_ddr_freq(0) / 1000000;
  34. while (pbsp->datarate_mhz_high) {
  35. if (pbsp->n_ranks == pdimm->n_ranks) {
  36. if (ddr_freq <= pbsp->datarate_mhz_high) {
  37. popts->clk_adjust = pbsp->clk_adjust;
  38. popts->wrlvl_start = pbsp->wrlvl_start;
  39. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  40. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  41. goto found;
  42. }
  43. pbsp_highest = pbsp;
  44. }
  45. pbsp++;
  46. }
  47. if (pbsp_highest) {
  48. printf("Error: board specific timing not found for %lu MT/s\n",
  49. ddr_freq);
  50. printf("Trying to use the highest speed (%u) parameters\n",
  51. pbsp_highest->datarate_mhz_high);
  52. popts->clk_adjust = pbsp_highest->clk_adjust;
  53. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  54. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  55. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  56. } else {
  57. panic("DIMM is not supported by this board");
  58. }
  59. found:
  60. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  61. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  62. popts->data_bus_width = 0; /* 64-bit data bus */
  63. popts->bstopre = 0; /* enable auto precharge */
  64. /*
  65. * Factors to consider for half-strength driver enable:
  66. * - number of DIMMs installed
  67. */
  68. popts->half_strength_driver_enable = 0;
  69. /*
  70. * Write leveling override
  71. */
  72. popts->wrlvl_override = 1;
  73. popts->wrlvl_sample = 0xf;
  74. /*
  75. * Rtt and Rtt_WR override
  76. */
  77. popts->rtt_override = 0;
  78. /* Enable ZQ calibration */
  79. popts->zq_en = 1;
  80. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  81. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  82. DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  83. /* optimize cpo for erratum A-009942 */
  84. popts->cpo_sample = 0x61;
  85. }
  86. #ifdef CONFIG_TFABOOT
  87. int fsl_initdram(void)
  88. {
  89. gd->ram_size = tfa_get_dram_size();
  90. if (!gd->ram_size)
  91. gd->ram_size = fsl_ddr_sdram_size();
  92. return 0;
  93. }
  94. #else
  95. int fsl_initdram(void)
  96. {
  97. phys_size_t dram_size;
  98. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  99. gd->ram_size = fsl_ddr_sdram_size();
  100. return 0;
  101. #else
  102. puts("Initializing DDR....using SPD\n");
  103. dram_size = fsl_ddr_sdram();
  104. #endif
  105. erratum_a008850_post();
  106. gd->ram_size = dram_size;
  107. return 0;
  108. }
  109. #endif