cpld.h 1.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor
  4. */
  5. #ifndef __CPLD_H__
  6. #define __CPLD_H__
  7. /*
  8. * CPLD register set of LS1046ARDB board-specific.
  9. * CPLD Revision: V2.1
  10. */
  11. struct cpld_data {
  12. u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
  13. u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
  14. u8 pcba_ver; /* 0x2 - PCBA Revision Register */
  15. u8 system_rst; /* 0x3 - system reset register */
  16. u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
  17. u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */
  18. u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */
  19. u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */
  20. u8 sysclk_sel; /* 0x8 - System clock POR Register */
  21. u8 uart_sel; /* 0x9 - UART1 Connection Control Register */
  22. u8 sd1refclk_sel; /* 0xA - */
  23. u8 rgmii_1588_sel; /* 0xB - */
  24. u8 reg_1588_clk_sel; /* 0xC - */
  25. u8 status_led; /* 0xD - */
  26. u8 global_rst; /* 0xE - */
  27. u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */
  28. u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */
  29. u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */
  30. };
  31. u8 cpld_read(unsigned int reg);
  32. void cpld_write(unsigned int reg, u8 value);
  33. void cpld_rev_bit(unsigned char *value);
  34. void cpld_select_core_volt(bool en_0v9);
  35. #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
  36. #define CPLD_WRITE(reg, value) \
  37. cpld_write(offsetof(struct cpld_data, reg), value)
  38. /* CPLD on IFC */
  39. #define CPLD_SW_MUX_BANK_SEL 0x40
  40. #define CPLD_BANK_SEL_MASK 0x07
  41. #define CPLD_BANK_SEL_ALTBANK 0x04
  42. #define CPLD_CFG_RCW_SRC_QSPI 0x044
  43. #define CPLD_CFG_RCW_SRC_SD 0x040
  44. #endif