ls1046aqds.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fdt_support.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <asm/arch/ppa.h>
  13. #include <asm/arch/fdt.h>
  14. #include <asm/arch/mmu.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  18. #include <ahci.h>
  19. #include <hwconfig.h>
  20. #include <mmc.h>
  21. #include <scsi.h>
  22. #include <fm_eth.h>
  23. #include <fsl_csu.h>
  24. #include <fsl_esdhc.h>
  25. #include <fsl_ifc.h>
  26. #include <fsl_sec.h>
  27. #include <spl.h>
  28. #include "../common/vid.h"
  29. #include "../common/qixis.h"
  30. #include "ls1046aqds_qixis.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #ifdef CONFIG_TFABOOT
  33. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  34. {
  35. "nor0",
  36. CONFIG_SYS_NOR0_CSPR,
  37. CONFIG_SYS_NOR0_CSPR_EXT,
  38. CONFIG_SYS_NOR_AMASK,
  39. CONFIG_SYS_NOR_CSOR,
  40. {
  41. CONFIG_SYS_NOR_FTIM0,
  42. CONFIG_SYS_NOR_FTIM1,
  43. CONFIG_SYS_NOR_FTIM2,
  44. CONFIG_SYS_NOR_FTIM3
  45. },
  46. },
  47. {
  48. "nor1",
  49. CONFIG_SYS_NOR1_CSPR,
  50. CONFIG_SYS_NOR1_CSPR_EXT,
  51. CONFIG_SYS_NOR_AMASK,
  52. CONFIG_SYS_NOR_CSOR,
  53. {
  54. CONFIG_SYS_NOR_FTIM0,
  55. CONFIG_SYS_NOR_FTIM1,
  56. CONFIG_SYS_NOR_FTIM2,
  57. CONFIG_SYS_NOR_FTIM3
  58. },
  59. },
  60. {
  61. "nand",
  62. CONFIG_SYS_NAND_CSPR,
  63. CONFIG_SYS_NAND_CSPR_EXT,
  64. CONFIG_SYS_NAND_AMASK,
  65. CONFIG_SYS_NAND_CSOR,
  66. {
  67. CONFIG_SYS_NAND_FTIM0,
  68. CONFIG_SYS_NAND_FTIM1,
  69. CONFIG_SYS_NAND_FTIM2,
  70. CONFIG_SYS_NAND_FTIM3
  71. },
  72. },
  73. {
  74. "fpga",
  75. CONFIG_SYS_FPGA_CSPR,
  76. CONFIG_SYS_FPGA_CSPR_EXT,
  77. CONFIG_SYS_FPGA_AMASK,
  78. CONFIG_SYS_FPGA_CSOR,
  79. {
  80. CONFIG_SYS_FPGA_FTIM0,
  81. CONFIG_SYS_FPGA_FTIM1,
  82. CONFIG_SYS_FPGA_FTIM2,
  83. CONFIG_SYS_FPGA_FTIM3
  84. },
  85. }
  86. };
  87. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  88. {
  89. "nand",
  90. CONFIG_SYS_NAND_CSPR,
  91. CONFIG_SYS_NAND_CSPR_EXT,
  92. CONFIG_SYS_NAND_AMASK,
  93. CONFIG_SYS_NAND_CSOR,
  94. {
  95. CONFIG_SYS_NAND_FTIM0,
  96. CONFIG_SYS_NAND_FTIM1,
  97. CONFIG_SYS_NAND_FTIM2,
  98. CONFIG_SYS_NAND_FTIM3
  99. },
  100. },
  101. {
  102. "nor0",
  103. CONFIG_SYS_NOR0_CSPR,
  104. CONFIG_SYS_NOR0_CSPR_EXT,
  105. CONFIG_SYS_NOR_AMASK,
  106. CONFIG_SYS_NOR_CSOR,
  107. {
  108. CONFIG_SYS_NOR_FTIM0,
  109. CONFIG_SYS_NOR_FTIM1,
  110. CONFIG_SYS_NOR_FTIM2,
  111. CONFIG_SYS_NOR_FTIM3
  112. },
  113. },
  114. {
  115. "nor1",
  116. CONFIG_SYS_NOR1_CSPR,
  117. CONFIG_SYS_NOR1_CSPR_EXT,
  118. CONFIG_SYS_NOR_AMASK,
  119. CONFIG_SYS_NOR_CSOR,
  120. {
  121. CONFIG_SYS_NOR_FTIM0,
  122. CONFIG_SYS_NOR_FTIM1,
  123. CONFIG_SYS_NOR_FTIM2,
  124. CONFIG_SYS_NOR_FTIM3
  125. },
  126. },
  127. {
  128. "fpga",
  129. CONFIG_SYS_FPGA_CSPR,
  130. CONFIG_SYS_FPGA_CSPR_EXT,
  131. CONFIG_SYS_FPGA_AMASK,
  132. CONFIG_SYS_FPGA_CSOR,
  133. {
  134. CONFIG_SYS_FPGA_FTIM0,
  135. CONFIG_SYS_FPGA_FTIM1,
  136. CONFIG_SYS_FPGA_FTIM2,
  137. CONFIG_SYS_FPGA_FTIM3
  138. },
  139. }
  140. };
  141. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  142. {
  143. enum boot_src src = get_boot_src();
  144. if (src == BOOT_SOURCE_IFC_NAND)
  145. regs_info->regs = ifc_cfg_nand_boot;
  146. else
  147. regs_info->regs = ifc_cfg_nor_boot;
  148. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  149. }
  150. #endif
  151. enum {
  152. MUX_TYPE_GPIO,
  153. };
  154. int checkboard(void)
  155. {
  156. #ifdef CONFIG_TFABOOT
  157. enum boot_src src = get_boot_src();
  158. #endif
  159. char buf[64];
  160. #ifndef CONFIG_SD_BOOT
  161. u8 sw;
  162. #endif
  163. puts("Board: LS1046AQDS, boot from ");
  164. #ifdef CONFIG_TFABOOT
  165. if (src == BOOT_SOURCE_SD_MMC)
  166. puts("SD\n");
  167. else {
  168. #endif
  169. #ifdef CONFIG_SD_BOOT
  170. puts("SD\n");
  171. #else
  172. sw = QIXIS_READ(brdcfg[0]);
  173. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  174. if (sw < 0x8)
  175. printf("vBank: %d\n", sw);
  176. else if (sw == 0x8)
  177. puts("PromJet\n");
  178. else if (sw == 0x9)
  179. puts("NAND\n");
  180. else if (sw == 0xF)
  181. printf("QSPI\n");
  182. else
  183. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  184. #endif
  185. #ifdef CONFIG_TFABOOT
  186. }
  187. #endif
  188. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  189. QIXIS_READ(id), QIXIS_READ(arch));
  190. printf("FPGA: v%d (%s), build %d\n",
  191. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  192. (int)qixis_read_minor());
  193. return 0;
  194. }
  195. bool if_board_diff_clk(void)
  196. {
  197. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  198. return diff_conf & 0x40;
  199. }
  200. unsigned long get_board_sys_clk(void)
  201. {
  202. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  203. switch (sysclk_conf & 0x0f) {
  204. case QIXIS_SYSCLK_64:
  205. return 64000000;
  206. case QIXIS_SYSCLK_83:
  207. return 83333333;
  208. case QIXIS_SYSCLK_100:
  209. return 100000000;
  210. case QIXIS_SYSCLK_125:
  211. return 125000000;
  212. case QIXIS_SYSCLK_133:
  213. return 133333333;
  214. case QIXIS_SYSCLK_150:
  215. return 150000000;
  216. case QIXIS_SYSCLK_160:
  217. return 160000000;
  218. case QIXIS_SYSCLK_166:
  219. return 166666666;
  220. }
  221. return 66666666;
  222. }
  223. unsigned long get_board_ddr_clk(void)
  224. {
  225. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  226. if (if_board_diff_clk())
  227. return get_board_sys_clk();
  228. switch ((ddrclk_conf & 0x30) >> 4) {
  229. case QIXIS_DDRCLK_100:
  230. return 100000000;
  231. case QIXIS_DDRCLK_125:
  232. return 125000000;
  233. case QIXIS_DDRCLK_133:
  234. return 133333333;
  235. }
  236. return 66666666;
  237. }
  238. #ifdef CONFIG_LPUART
  239. u32 get_lpuart_clk(void)
  240. {
  241. return gd->bus_clk;
  242. }
  243. #endif
  244. int select_i2c_ch_pca9547(u8 ch)
  245. {
  246. int ret;
  247. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  248. if (ret) {
  249. puts("PCA: failed to select proper channel\n");
  250. return ret;
  251. }
  252. return 0;
  253. }
  254. int dram_init(void)
  255. {
  256. /*
  257. * When resuming from deep sleep, the I2C channel may not be
  258. * in the default channel. So, switch to the default channel
  259. * before accessing DDR SPD.
  260. */
  261. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  262. fsl_initdram();
  263. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  264. defined(CONFIG_SPL_BUILD)
  265. /* This will break-before-make MMU for DDR */
  266. update_early_mmu_table();
  267. #endif
  268. return 0;
  269. }
  270. int i2c_multiplexer_select_vid_channel(u8 channel)
  271. {
  272. return select_i2c_ch_pca9547(channel);
  273. }
  274. int board_early_init_f(void)
  275. {
  276. #ifdef CONFIG_HAS_FSL_XHCI_USB
  277. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  278. u32 usb_pwrfault;
  279. #endif
  280. #ifdef CONFIG_LPUART
  281. u8 uart;
  282. #endif
  283. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  284. i2c_early_init_f();
  285. #endif
  286. fsl_lsch2_early_init_f();
  287. #ifdef CONFIG_HAS_FSL_XHCI_USB
  288. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  289. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  290. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  291. SCFG_USBPWRFAULT_USB3_SHIFT) |
  292. (SCFG_USBPWRFAULT_DEDICATED <<
  293. SCFG_USBPWRFAULT_USB2_SHIFT) |
  294. (SCFG_USBPWRFAULT_SHARED <<
  295. SCFG_USBPWRFAULT_USB1_SHIFT);
  296. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  297. #endif
  298. #ifdef CONFIG_LPUART
  299. /* We use lpuart0 as system console */
  300. uart = QIXIS_READ(brdcfg[14]);
  301. uart &= ~CFG_UART_MUX_MASK;
  302. uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
  303. QIXIS_WRITE(brdcfg[14], uart);
  304. #endif
  305. return 0;
  306. }
  307. #ifdef CONFIG_FSL_DEEP_SLEEP
  308. /* determine if it is a warm boot */
  309. bool is_warm_boot(void)
  310. {
  311. #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
  312. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  313. if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
  314. return 1;
  315. return 0;
  316. }
  317. #endif
  318. int config_board_mux(int ctrl_type)
  319. {
  320. u8 reg14;
  321. reg14 = QIXIS_READ(brdcfg[14]);
  322. switch (ctrl_type) {
  323. case MUX_TYPE_GPIO:
  324. reg14 = (reg14 & (~0x6)) | 0x2;
  325. break;
  326. default:
  327. puts("Unsupported mux interface type\n");
  328. return -1;
  329. }
  330. QIXIS_WRITE(brdcfg[14], reg14);
  331. return 0;
  332. }
  333. int config_serdes_mux(void)
  334. {
  335. return 0;
  336. }
  337. #ifdef CONFIG_MISC_INIT_R
  338. int misc_init_r(void)
  339. {
  340. if (hwconfig("gpio"))
  341. config_board_mux(MUX_TYPE_GPIO);
  342. return 0;
  343. }
  344. #endif
  345. int board_init(void)
  346. {
  347. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  348. #ifdef CONFIG_SYS_FSL_SERDES
  349. config_serdes_mux();
  350. #endif
  351. if (adjust_vdd(0))
  352. printf("Warning: Adjusting core voltage failed.\n");
  353. #ifdef CONFIG_FSL_LS_PPA
  354. ppa_init();
  355. #endif
  356. #ifdef CONFIG_NXP_ESBC
  357. /*
  358. * In case of Secure Boot, the IBR configures the SMMU
  359. * to allow only Secure transactions.
  360. * SMMU must be reset in bypass mode.
  361. * Set the ClientPD bit and Clear the USFCFG Bit
  362. */
  363. u32 val;
  364. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  365. out_le32(SMMU_SCR0, val);
  366. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  367. out_le32(SMMU_NSCR0, val);
  368. #endif
  369. #ifdef CONFIG_FSL_CAAM
  370. sec_init();
  371. #endif
  372. return 0;
  373. }
  374. #ifdef CONFIG_OF_BOARD_SETUP
  375. int ft_board_setup(void *blob, bd_t *bd)
  376. {
  377. u64 base[CONFIG_NR_DRAM_BANKS];
  378. u64 size[CONFIG_NR_DRAM_BANKS];
  379. u8 reg;
  380. /* fixup DT for the two DDR banks */
  381. base[0] = gd->bd->bi_dram[0].start;
  382. size[0] = gd->bd->bi_dram[0].size;
  383. base[1] = gd->bd->bi_dram[1].start;
  384. size[1] = gd->bd->bi_dram[1].size;
  385. fdt_fixup_memory_banks(blob, base, size, 2);
  386. ft_cpu_setup(blob, bd);
  387. #ifdef CONFIG_SYS_DPAA_FMAN
  388. fdt_fixup_fman_ethernet(blob);
  389. fdt_fixup_board_enet(blob);
  390. #endif
  391. fdt_fixup_icid(blob);
  392. reg = QIXIS_READ(brdcfg[0]);
  393. reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  394. /* Disable IFC if QSPI is enabled */
  395. if (reg == 0xF)
  396. do_fixup_by_compat(blob, "fsl,ifc",
  397. "status", "disabled", 8 + 1, 1);
  398. return 0;
  399. }
  400. #endif
  401. u8 flash_read8(void *addr)
  402. {
  403. return __raw_readb(addr + 1);
  404. }
  405. void flash_write16(u16 val, void *addr)
  406. {
  407. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  408. __raw_writew(shftval, addr);
  409. }
  410. u16 flash_read16(void *addr)
  411. {
  412. u16 val = __raw_readw(addr);
  413. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  414. }
  415. #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  416. void *env_sf_get_env_addr(void)
  417. {
  418. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  419. }
  420. #endif