ddr.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #ifdef CONFIG_FSL_DEEP_SLEEP
  9. #include <fsl_sleep.h>
  10. #endif
  11. #include <asm/arch/clock.h>
  12. #include "ddr.h"
  13. DECLARE_GLOBAL_DATA_PTR;
  14. void fsl_ddr_board_options(memctl_options_t *popts,
  15. dimm_params_t *pdimm,
  16. unsigned int ctrl_num)
  17. {
  18. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  19. ulong ddr_freq;
  20. if (ctrl_num > 3) {
  21. printf("Not supported controller number %d\n", ctrl_num);
  22. return;
  23. }
  24. if (!pdimm->n_ranks)
  25. return;
  26. pbsp = udimms[0];
  27. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  28. * freqency and n_banks specified in board_specific_parameters table.
  29. */
  30. ddr_freq = get_ddr_freq(0) / 1000000;
  31. while (pbsp->datarate_mhz_high) {
  32. if (pbsp->n_ranks == pdimm->n_ranks) {
  33. if (ddr_freq <= pbsp->datarate_mhz_high) {
  34. popts->clk_adjust = pbsp->clk_adjust;
  35. popts->wrlvl_start = pbsp->wrlvl_start;
  36. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  37. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  38. goto found;
  39. }
  40. pbsp_highest = pbsp;
  41. }
  42. pbsp++;
  43. }
  44. if (pbsp_highest) {
  45. printf("Error: board specific timing not found for %lu MT/s\n",
  46. ddr_freq);
  47. printf("Trying to use the highest speed (%u) parameters\n",
  48. pbsp_highest->datarate_mhz_high);
  49. popts->clk_adjust = pbsp_highest->clk_adjust;
  50. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  51. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  52. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  53. } else {
  54. panic("DIMM is not supported by this board");
  55. }
  56. found:
  57. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  58. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  59. popts->data_bus_width = 0; /* 64b data bus */
  60. popts->otf_burst_chop_en = 0;
  61. popts->burst_length = DDR_BL8;
  62. popts->bstopre = 0; /* enable auto precharge */
  63. popts->half_strength_driver_enable = 0;
  64. /*
  65. * Write leveling override
  66. */
  67. popts->wrlvl_override = 1;
  68. popts->wrlvl_sample = 0xf;
  69. /*
  70. * Rtt and Rtt_WR override
  71. */
  72. popts->rtt_override = 0;
  73. /* Enable ZQ calibration */
  74. popts->zq_en = 1;
  75. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  76. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  77. DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  78. /* optimize cpo for erratum A-009942 */
  79. popts->cpo_sample = 0x70;
  80. }
  81. #ifdef CONFIG_TFABOOT
  82. int fsl_initdram(void)
  83. {
  84. gd->ram_size = tfa_get_dram_size();
  85. if (!gd->ram_size)
  86. gd->ram_size = fsl_ddr_sdram_size();
  87. return 0;
  88. }
  89. #else
  90. int fsl_initdram(void)
  91. {
  92. phys_size_t dram_size;
  93. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  94. gd->ram_size = fsl_ddr_sdram_size();
  95. return 0;
  96. #else
  97. puts("Initializing DDR....using SPD\n");
  98. dram_size = fsl_ddr_sdram();
  99. #endif
  100. #ifdef CONFIG_FSL_DEEP_SLEEP
  101. fsl_dp_ddr_restore();
  102. #endif
  103. erratum_a008850_post();
  104. gd->ram_size = dram_size;
  105. return 0;
  106. }
  107. #endif