ls1046afrwy.c 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fdt_support.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/soc.h>
  12. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  13. #include <hwconfig.h>
  14. #include <ahci.h>
  15. #include <mmc.h>
  16. #include <scsi.h>
  17. #include <fm_eth.h>
  18. #include <fsl_csu.h>
  19. #include <fsl_esdhc.h>
  20. #include <fsl_sec.h>
  21. #include <fsl_dspi.h>
  22. #define LS1046A_PORSR1_REG 0x1EE0000
  23. #define BOOT_SRC_SD 0x20000000
  24. #define BOOT_SRC_MASK 0xFF800000
  25. #define BOARD_REV_GPIO 13
  26. #define USB2_SEL_MASK 0x00000100
  27. #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
  28. (((word) & 0x00ff0000) >> 8) | \
  29. (((word) & 0x0000ff00) << 8) | \
  30. (((word) & 0x000000ff) << 24))
  31. #define SPI_MCR_REG 0x2100000
  32. DECLARE_GLOBAL_DATA_PTR;
  33. int select_i2c_ch_pca9547(u8 ch)
  34. {
  35. int ret;
  36. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  37. if (ret) {
  38. puts("PCA: failed to select proper channel\n");
  39. return ret;
  40. }
  41. return 0;
  42. }
  43. static inline void demux_select_usb2(void)
  44. {
  45. u32 val;
  46. struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
  47. val = in_be32(&pgpio->gpdir);
  48. val |= USB2_SEL_MASK;
  49. out_be32(&pgpio->gpdir, val);
  50. val = in_be32(&pgpio->gpdat);
  51. val |= USB2_SEL_MASK;
  52. out_be32(&pgpio->gpdat, val);
  53. }
  54. static inline void set_spi_cs_signal_inactive(void)
  55. {
  56. /* default: all CS signals inactive state is high */
  57. uint mcr_val;
  58. uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  59. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  60. mcr_val = in_be32(SPI_MCR_REG);
  61. mcr_val |= DSPI_MCR_HALT;
  62. out_be32(SPI_MCR_REG, mcr_val);
  63. out_be32(SPI_MCR_REG, mcr_cfg_val);
  64. mcr_val = in_be32(SPI_MCR_REG);
  65. mcr_val &= ~DSPI_MCR_HALT;
  66. out_be32(SPI_MCR_REG, mcr_val);
  67. }
  68. int board_early_init_f(void)
  69. {
  70. fsl_lsch2_early_init_f();
  71. return 0;
  72. }
  73. static inline uint8_t get_board_version(void)
  74. {
  75. u8 val;
  76. struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  77. val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
  78. return val;
  79. }
  80. int checkboard(void)
  81. {
  82. static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
  83. u32 boot_src;
  84. u8 rev;
  85. rev = get_board_version();
  86. switch (rev) {
  87. case 0x00:
  88. puts("Board: LS1046AFRWY, Rev: A, boot from ");
  89. break;
  90. case 0x01:
  91. puts("Board: LS1046AFRWY, Rev: B, boot from ");
  92. break;
  93. default:
  94. puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
  95. break;
  96. }
  97. boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
  98. if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
  99. puts("SD\n");
  100. else
  101. puts("QSPI\n");
  102. printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
  103. return 0;
  104. }
  105. int board_init(void)
  106. {
  107. #ifdef CONFIG_NXP_ESBC
  108. /*
  109. * In case of Secure Boot, the IBR configures the SMMU
  110. * to allow only Secure transactions.
  111. * SMMU must be reset in bypass mode.
  112. * Set the ClientPD bit and Clear the USFCFG Bit
  113. */
  114. u32 val;
  115. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  116. out_le32(SMMU_SCR0, val);
  117. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  118. out_le32(SMMU_NSCR0, val);
  119. #endif
  120. #ifdef CONFIG_FSL_CAAM
  121. sec_init();
  122. #endif
  123. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  124. return 0;
  125. }
  126. int board_setup_core_volt(u32 vdd)
  127. {
  128. return 0;
  129. }
  130. void config_board_mux(void)
  131. {
  132. #ifdef CONFIG_HAS_FSL_XHCI_USB
  133. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  134. u32 usb_pwrfault;
  135. /*
  136. * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
  137. * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
  138. */
  139. out_be32(&scfg->rcwpmuxcr0, 0x3300);
  140. #ifdef CONFIG_HAS_FSL_IIC3
  141. /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
  142. out_be32(&scfg->rcwpmuxcr0, 0x0000);
  143. #endif
  144. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  145. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  146. SCFG_USBPWRFAULT_USB3_SHIFT) |
  147. (SCFG_USBPWRFAULT_DEDICATED <<
  148. SCFG_USBPWRFAULT_USB2_SHIFT) |
  149. (SCFG_USBPWRFAULT_SHARED <<
  150. SCFG_USBPWRFAULT_USB1_SHIFT);
  151. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  152. #ifndef CONFIG_HAS_FSL_IIC3
  153. /*
  154. * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
  155. * to select I2C3_USB2_SEL_IO
  156. * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
  157. * I2C3 header (default)
  158. * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
  159. * USB2 port
  160. * programmed to select USB2 by setting GPIO3_23 output to one
  161. */
  162. demux_select_usb2();
  163. #endif
  164. #endif
  165. set_spi_cs_signal_inactive();
  166. }
  167. #ifdef CONFIG_MISC_INIT_R
  168. int misc_init_r(void)
  169. {
  170. config_board_mux();
  171. return 0;
  172. }
  173. #endif
  174. int ft_board_setup(void *blob, bd_t *bd)
  175. {
  176. u64 base[CONFIG_NR_DRAM_BANKS];
  177. u64 size[CONFIG_NR_DRAM_BANKS];
  178. /* fixup DT for the two DDR banks */
  179. base[0] = gd->bd->bi_dram[0].start;
  180. size[0] = gd->bd->bi_dram[0].size;
  181. base[1] = gd->bd->bi_dram[1].start;
  182. size[1] = gd->bd->bi_dram[1].size;
  183. fdt_fixup_memory_banks(blob, base, size, 2);
  184. ft_cpu_setup(blob, bd);
  185. #ifdef CONFIG_SYS_DPAA_FMAN
  186. fdt_fixup_fman_ethernet(blob);
  187. #endif
  188. fdt_fixup_icid(blob);
  189. return 0;
  190. }