README 4.8 KB

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  1. Overview
  2. --------
  3. The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
  4. LS1021A SoC Overview
  5. ------------------
  6. The QorIQ LS1 family, which includes the LS1021A communications processor,
  7. is built on Layerscape architecture, the industry's first software-aware,
  8. core-agnostic networking architecture to offer unprecedented efficiency
  9. and scale.
  10. A member of the value-performance tier, the QorIQ LS1021A processor provides
  11. extensive integration and power efficiency for fanless, small form factor
  12. enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
  13. running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
  14. performance of over 6,000, as well as virtualization support, advanced
  15. security features and the broadest array of high-speed interconnects and
  16. optimized peripheral features ever offered in a sub-3 W processor.
  17. The QorIQ LS1021A processor features an integrated LCD controller,
  18. CAN controller for implementing industrial protocols, DDR3L/4 running
  19. up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
  20. protection on both L1 and L2 caches. The LS1021A processor is pin- and
  21. software-compatible with the QorIQ LS1020A and LS1022A processors.
  22. The LS1021A SoC includes the following function and features:
  23. - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
  24. - Dual high-preformance ARM Cortex-A7 cores, each core includes:
  25. - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
  26. - 512 Kbyte shared coherent L2 Cache (with ECC protection)
  27. - NEON Co-processor (per core)
  28. - 40-bit physical addressing
  29. - Vector floating-point support
  30. - ARM Core-Link CCI-400 Cache Coherent Interconnect
  31. - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
  32. supporting speeds up to 1600Mtps
  33. - ECC and interleaving support
  34. - VeTSEC Ethernet complex
  35. - Up to 3x virtualized 10/100/1000 Ethernet controllers
  36. - MII, RMII, RGMII, and SGMII support
  37. - QoS, lossless flow control, and IEEE 1588 support
  38. - 4-lane 6GHz SerDes
  39. - High speed interconnect (4 SerDes lanes with are muxed for these protocol)
  40. - Two PCI Express Gen2 controllers running at up to 5 GHz
  41. - One Serial ATA 3.0 supporting 6 GT/s operation
  42. - Two SGMII interfaces supporting 1000 Mbps
  43. - Additional peripheral interfaces
  44. - One high-speed USB 3.0 controller with integrated PHY and one high-speed
  45. USB 2.00 controller with ULPI
  46. - Integrated flash controller (IFC) with 16-bit interface
  47. - Quad SPI NOR Flash
  48. - One enhanced Secure digital host controller
  49. - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
  50. - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
  51. UARTs
  52. - Three I2C controllers
  53. - Eight FlexTimers four supporting PWM and four FlexCAN ports
  54. - Four GPIO controllers supporting up to 109 general purpose I/O signals
  55. - Integrated advanced audio block:
  56. - Four synchronous audio interfaces (SAI)
  57. - Sony/Philips Digital Interconnect Format (SPDIF)
  58. - Asynchronous Sample Rate Converter (ASRC)
  59. - Hardware based crypto offload engine
  60. - IPSec forwarding at up to 1Gbps
  61. - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
  62. - Public key hardware accelerator
  63. - True Random Number Generator (NIST Certified)
  64. - Advanced Encryption Standard Accelerators (AESA)
  65. - Data Encryption Standard Accelerators
  66. - QUICC Engine ULite block
  67. - Two universal communication controllers (TDM and HDLC) supporting 64
  68. multichannels, each running at 64 Kbps
  69. - Support for 256 channels of HDLC
  70. - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
  71. LS1021ATWR board Overview
  72. -------------------------
  73. - DDR Controller
  74. - Supports rates of up to 1600 MHz data-rate
  75. - Supports one DDR3LP SDRAM.
  76. - IFC/Local Bus
  77. - NOR: 128MB 16-bit NOR Flash
  78. - Ethernet
  79. - Three on-board RGMII 10/100/1G ethernet ports.
  80. - CPLD
  81. - Clocks
  82. - System and DDR clock (SYSCLK, DDRCLK)
  83. - SERDES clocks
  84. - Power Supplies
  85. - SDHC
  86. - SDHC/SDXC connector
  87. - Other IO
  88. - One Serial port
  89. - Three I2C ports
  90. Memory map
  91. -----------
  92. The addresses in brackets are physical addresses.
  93. Start Address End Address Description Size
  94. 0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
  95. 0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
  96. 0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
  97. 0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
  98. 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
  99. 0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
  100. 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
  101. 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
  102. LS1021a rev1.0 Soc specific Options/Settings
  103. --------------------------------------------
  104. If the LS1021a Soc is rev1.0, you need modify the configure file.
  105. Add the following define in include/configs/ls1021atwr.h:
  106. #define CONFIG_SKIP_LOWLEVEL_INIT