ddr.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include "ddr.h"
  11. DECLARE_GLOBAL_DATA_PTR;
  12. void fsl_ddr_board_options(memctl_options_t *popts,
  13. dimm_params_t *pdimm,
  14. unsigned int ctrl_num)
  15. {
  16. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  17. ulong ddr_freq;
  18. if (ctrl_num > 3) {
  19. printf("Not supported controller number %d\n", ctrl_num);
  20. return;
  21. }
  22. if (!pdimm->n_ranks)
  23. return;
  24. pbsp = udimms[0];
  25. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  26. * freqency and n_banks specified in board_specific_parameters table.
  27. */
  28. ddr_freq = get_ddr_freq(0) / 1000000;
  29. while (pbsp->datarate_mhz_high) {
  30. if (pbsp->n_ranks == pdimm->n_ranks) {
  31. if (ddr_freq <= pbsp->datarate_mhz_high) {
  32. popts->clk_adjust = pbsp->clk_adjust;
  33. popts->wrlvl_start = pbsp->wrlvl_start;
  34. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  35. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  36. popts->cpo_override = pbsp->cpo_override;
  37. popts->write_data_delay =
  38. pbsp->write_data_delay;
  39. goto found;
  40. }
  41. pbsp_highest = pbsp;
  42. }
  43. pbsp++;
  44. }
  45. if (pbsp_highest) {
  46. printf("Error: board specific timing not found for %lu MT/s\n",
  47. ddr_freq);
  48. printf("Trying to use the highest speed (%u) parameters\n",
  49. pbsp_highest->datarate_mhz_high);
  50. popts->clk_adjust = pbsp_highest->clk_adjust;
  51. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  52. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  53. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  54. } else {
  55. panic("DIMM is not supported by this board");
  56. }
  57. found:
  58. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  59. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  60. /* force DDR bus width to 32 bits */
  61. popts->data_bus_width = 1;
  62. popts->otf_burst_chop_en = 0;
  63. popts->burst_length = DDR_BL8;
  64. /*
  65. * Factors to consider for half-strength driver enable:
  66. * - number of DIMMs installed
  67. */
  68. popts->half_strength_driver_enable = 1;
  69. /*
  70. * Write leveling override
  71. */
  72. popts->wrlvl_override = 1;
  73. popts->wrlvl_sample = 0xf;
  74. /*
  75. * Rtt and Rtt_WR override
  76. */
  77. popts->rtt_override = 0;
  78. /* Enable ZQ calibration */
  79. popts->zq_en = 1;
  80. #ifdef CONFIG_SYS_FSL_DDR4
  81. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  82. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  83. DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
  84. #else
  85. popts->cswl_override = DDR_CSWL_CS0;
  86. /* optimize cpo for erratum A-009942 */
  87. popts->cpo_sample = 0x58;
  88. /* DHC_EN =1, ODT = 75 Ohm */
  89. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  90. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  91. #endif
  92. }
  93. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  94. dimm_params_t ddr_raw_timing = {
  95. .n_ranks = 1,
  96. .rank_density = 1073741824u,
  97. .capacity = 1073741824u,
  98. .primary_sdram_width = 32,
  99. .ec_sdram_width = 0,
  100. .registered_dimm = 0,
  101. .mirrored_dimm = 0,
  102. .n_row_addr = 15,
  103. .n_col_addr = 10,
  104. .n_banks_per_sdram_device = 8,
  105. .edc_config = 0,
  106. .burst_lengths_bitmask = 0x0c,
  107. .tckmin_x_ps = 1071,
  108. .caslat_x = 0xfe << 4, /* 5,6,7,8 */
  109. .taa_ps = 13125,
  110. .twr_ps = 15000,
  111. .trcd_ps = 13125,
  112. .trrd_ps = 7500,
  113. .trp_ps = 13125,
  114. .tras_ps = 37500,
  115. .trc_ps = 50625,
  116. .trfc_ps = 160000,
  117. .twtr_ps = 7500,
  118. .trtp_ps = 7500,
  119. .refresh_rate_ps = 7800000,
  120. .tfaw_ps = 37500,
  121. };
  122. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  123. unsigned int controller_number,
  124. unsigned int dimm_number)
  125. {
  126. static const char dimm_model[] = "Fixed DDR on board";
  127. if (((controller_number == 0) && (dimm_number == 0)) ||
  128. ((controller_number == 1) && (dimm_number == 0))) {
  129. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  130. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  131. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  132. }
  133. return 0;
  134. }
  135. #endif
  136. #if defined(CONFIG_DEEP_SLEEP)
  137. void board_mem_sleep_setup(void)
  138. {
  139. void __iomem *qixis_base = (void *)QIXIS_BASE;
  140. /* does not provide HW signals for power management */
  141. clrbits_8(qixis_base + 0x21, 0x2);
  142. udelay(1);
  143. }
  144. #endif
  145. int fsl_initdram(void)
  146. {
  147. phys_size_t dram_size;
  148. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
  149. puts("Initializing DDR....using SPD\n");
  150. dram_size = fsl_ddr_sdram();
  151. #else
  152. dram_size = fsl_ddr_sdram_size();
  153. #endif
  154. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  155. fsl_dp_resume();
  156. #endif
  157. erratum_a008850_post();
  158. gd->ram_size = dram_size;
  159. return 0;
  160. }
  161. int dram_init_banksize(void)
  162. {
  163. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  164. gd->bd->bi_dram[0].size = gd->ram_size;
  165. return 0;
  166. }