eth.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <asm/io.h>
  9. #include <netdev.h>
  10. #include <fm_eth.h>
  11. #include <fsl_mdio.h>
  12. #include <malloc.h>
  13. #include <asm/types.h>
  14. #include <fsl_dtsec.h>
  15. #include <asm/arch/soc.h>
  16. #include <asm/arch-fsl-layerscape/config.h>
  17. #include <asm/arch-fsl-layerscape/immap_lsch2.h>
  18. #include <asm/arch/fsl_serdes.h>
  19. #include <net/pfe_eth/pfe_eth.h>
  20. #include <dm/platform_data/pfe_dm_eth.h>
  21. #include <i2c.h>
  22. #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
  23. static inline void ls1012ardb_reset_phy(void)
  24. {
  25. #ifdef CONFIG_TARGET_LS1012ARDB
  26. /* Through reset IO expander reset both RGMII and SGMII PHYs */
  27. i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
  28. i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
  29. mdelay(10);
  30. i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
  31. mdelay(10);
  32. i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
  33. mdelay(50);
  34. #endif
  35. }
  36. int pfe_eth_board_init(struct udevice *dev)
  37. {
  38. static int init_done;
  39. struct mii_dev *bus;
  40. struct pfe_mdio_info mac_mdio_info;
  41. struct pfe_eth_dev *priv = dev_get_priv(dev);
  42. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  43. int srds_s1 = in_be32(&gur->rcwsr[4]) &
  44. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  45. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  46. if (!init_done) {
  47. ls1012ardb_reset_phy();
  48. mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
  49. mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
  50. bus = pfe_mdio_init(&mac_mdio_info);
  51. if (!bus) {
  52. printf("Failed to register mdio\n");
  53. return -1;
  54. }
  55. init_done = 1;
  56. }
  57. pfe_set_mdio(priv->gemac_port,
  58. miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
  59. switch (srds_s1) {
  60. case 0x3508:
  61. if (!priv->gemac_port) {
  62. /* MAC1 */
  63. pfe_set_phy_address_mode(priv->gemac_port,
  64. CONFIG_PFE_EMAC1_PHY_ADDR,
  65. PHY_INTERFACE_MODE_SGMII);
  66. } else {
  67. /* MAC2 */
  68. pfe_set_phy_address_mode(priv->gemac_port,
  69. CONFIG_PFE_EMAC2_PHY_ADDR,
  70. PHY_INTERFACE_MODE_RGMII_TXID);
  71. }
  72. break;
  73. case 0x2208:
  74. if (!priv->gemac_port) {
  75. /* MAC1 */
  76. pfe_set_phy_address_mode(priv->gemac_port,
  77. CONFIG_PFE_EMAC1_PHY_ADDR,
  78. PHY_INTERFACE_MODE_SGMII_2500);
  79. } else {
  80. /* MAC2 */
  81. pfe_set_phy_address_mode(priv->gemac_port,
  82. CONFIG_PFE_EMAC2_PHY_ADDR,
  83. PHY_INTERFACE_MODE_SGMII_2500);
  84. }
  85. break;
  86. default:
  87. printf("unsupported SerDes PRCTL= %d\n", srds_s1);
  88. break;
  89. }
  90. return 0;
  91. }
  92. static struct pfe_eth_pdata pfe_pdata0 = {
  93. .pfe_eth_pdata_mac = {
  94. .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
  95. .phy_interface = 0,
  96. },
  97. .pfe_ddr_addr = {
  98. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  99. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  100. },
  101. };
  102. static struct pfe_eth_pdata pfe_pdata1 = {
  103. .pfe_eth_pdata_mac = {
  104. .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
  105. .phy_interface = 1,
  106. },
  107. .pfe_ddr_addr = {
  108. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  109. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  110. },
  111. };
  112. U_BOOT_DEVICE(ls1012a_pfe0) = {
  113. .name = "pfe_eth",
  114. .platdata = &pfe_pdata0,
  115. };
  116. U_BOOT_DEVICE(ls1012a_pfe1) = {
  117. .name = "pfe_eth",
  118. .platdata = &pfe_pdata1,
  119. };