spl.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <errno.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/ddr.h>
  12. #include <asm/arch/imx8mq_pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/gpio.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <mmc.h>
  20. #include <power/pmic.h>
  21. #include <power/pfuze100_pmic.h>
  22. #include <spl.h>
  23. #include "../common/pfuze.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. extern struct dram_timing_info dram_timing_b0;
  26. static void spl_dram_init(void)
  27. {
  28. /* ddr init */
  29. if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
  30. ddr_init(&dram_timing);
  31. else
  32. ddr_init(&dram_timing_b0);
  33. }
  34. #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  35. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  36. static struct i2c_pads_info i2c_pad_info1 = {
  37. .scl = {
  38. .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
  39. .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  40. .gp = IMX_GPIO_NR(5, 14),
  41. },
  42. .sda = {
  43. .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
  44. .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  45. .gp = IMX_GPIO_NR(5, 15),
  46. },
  47. };
  48. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
  49. #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  50. #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  51. int board_mmc_getcd(struct mmc *mmc)
  52. {
  53. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  54. int ret = 0;
  55. switch (cfg->esdhc_base) {
  56. case USDHC1_BASE_ADDR:
  57. ret = 1;
  58. break;
  59. case USDHC2_BASE_ADDR:
  60. ret = !gpio_get_value(USDHC2_CD_GPIO);
  61. return ret;
  62. }
  63. return 1;
  64. }
  65. #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  66. PAD_CTL_FSEL2)
  67. #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  68. static iomux_v3_cfg_t const usdhc1_pads[] = {
  69. IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70. IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71. IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72. IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73. IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74. IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75. IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76. IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  80. };
  81. static iomux_v3_cfg_t const usdhc2_pads[] = {
  82. IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  83. IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  84. IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  85. IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  86. IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
  87. IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  88. IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  89. IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  90. };
  91. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  92. {USDHC1_BASE_ADDR, 0, 8},
  93. {USDHC2_BASE_ADDR, 0, 4},
  94. };
  95. int board_mmc_init(bd_t *bis)
  96. {
  97. int i, ret;
  98. /*
  99. * According to the board_mmc_init() the following map is done:
  100. * (U-Boot device node) (Physical Port)
  101. * mmc0 USDHC1
  102. * mmc1 USDHC2
  103. */
  104. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  105. switch (i) {
  106. case 0:
  107. init_clk_usdhc(0);
  108. usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
  109. imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
  110. ARRAY_SIZE(usdhc1_pads));
  111. gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
  112. gpio_direction_output(USDHC1_PWR_GPIO, 0);
  113. udelay(500);
  114. gpio_direction_output(USDHC1_PWR_GPIO, 1);
  115. break;
  116. case 1:
  117. init_clk_usdhc(1);
  118. usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
  119. imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
  120. ARRAY_SIZE(usdhc2_pads));
  121. gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
  122. gpio_direction_output(USDHC2_PWR_GPIO, 0);
  123. udelay(500);
  124. gpio_direction_output(USDHC2_PWR_GPIO, 1);
  125. break;
  126. default:
  127. printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
  128. return -EINVAL;
  129. }
  130. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  131. if (ret)
  132. return ret;
  133. }
  134. return 0;
  135. }
  136. #ifdef CONFIG_POWER
  137. #define I2C_PMIC 0
  138. int power_init_board(void)
  139. {
  140. struct pmic *p;
  141. int ret;
  142. unsigned int reg;
  143. ret = power_pfuze100_init(I2C_PMIC);
  144. if (ret)
  145. return -ENODEV;
  146. p = pmic_get("PFUZE100");
  147. ret = pmic_probe(p);
  148. if (ret)
  149. return -ENODEV;
  150. pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  151. printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  152. pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
  153. if ((reg & 0x3f) != 0x18) {
  154. reg &= ~0x3f;
  155. reg |= 0x18;
  156. pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
  157. }
  158. ret = pfuze_mode_init(p, APS_PFM);
  159. if (ret < 0)
  160. return ret;
  161. /* set SW3A standby mode to off */
  162. pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
  163. reg &= ~0xf;
  164. reg |= APS_OFF;
  165. pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
  166. return 0;
  167. }
  168. #endif
  169. void spl_board_init(void)
  170. {
  171. puts("Normal Boot\n");
  172. }
  173. #ifdef CONFIG_SPL_LOAD_FIT
  174. int board_fit_config_name_match(const char *name)
  175. {
  176. /* Just empty function now - can't decide what to choose */
  177. debug("%s: %s\n", __func__, name);
  178. return 0;
  179. }
  180. #endif
  181. void board_init_f(ulong dummy)
  182. {
  183. int ret;
  184. /* Clear global data */
  185. memset((void *)gd, 0, sizeof(gd_t));
  186. arch_cpu_init();
  187. init_uart_clk(0);
  188. board_early_init_f();
  189. timer_init();
  190. preloader_console_init();
  191. /* Clear the BSS. */
  192. memset(__bss_start, 0, __bss_end - __bss_start);
  193. ret = spl_init();
  194. if (ret) {
  195. debug("spl_init() failed: %d\n", ret);
  196. hang();
  197. }
  198. enable_tzc380();
  199. /* Adjust pmic voltage to 1.0V for 800M */
  200. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  201. power_init_board();
  202. /* DDR initialization */
  203. spl_dram_init();
  204. board_init_r(NULL, 0);
  205. }