lpddr4_timing.c 31 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <linux/kernel.h>
  6. #include <common.h>
  7. #include <asm/arch/ddr.h>
  8. #include <asm/arch/lpddr4_define.h>
  9. #define WR_POST_EXT_3200 /* recommened to define */
  10. struct dram_cfg_param lpddr4_ddrc_cfg[] = {
  11. /* Start to config, default 3200mbps */
  12. { DDRC_DBG1(0), 0x00000001 },
  13. { DDRC_PWRCTL(0), 0x00000001 },
  14. { DDRC_MSTR(0), 0xa3080020 },
  15. { DDRC_MSTR2(0), 0x00000000 },
  16. { DDRC_RFSHTMG(0), 0x006100E0 },
  17. { DDRC_INIT0(0), 0xC003061B },
  18. { DDRC_INIT1(0), 0x009D0000 },
  19. { DDRC_INIT3(0), 0x00D4002D },
  20. #ifdef WR_POST_EXT_3200
  21. { DDRC_INIT4(0), 0x00330008 },
  22. #else
  23. { DDRC_INIT4(0), 0x00310008 },
  24. #endif
  25. { DDRC_INIT6(0), 0x0066004a },
  26. { DDRC_INIT7(0), 0x0006004a },
  27. { DDRC_DRAMTMG0(0), 0x1A201B22 },
  28. { DDRC_DRAMTMG1(0), 0x00060633 },
  29. { DDRC_DRAMTMG3(0), 0x00C0C000 },
  30. { DDRC_DRAMTMG4(0), 0x0F04080F },
  31. { DDRC_DRAMTMG5(0), 0x02040C0C },
  32. { DDRC_DRAMTMG6(0), 0x01010007 },
  33. { DDRC_DRAMTMG7(0), 0x00000401 },
  34. { DDRC_DRAMTMG12(0), 0x00020600 },
  35. { DDRC_DRAMTMG13(0), 0x0C100002 },
  36. { DDRC_DRAMTMG14(0), 0x000000E6 },
  37. { DDRC_DRAMTMG17(0), 0x00A00050 },
  38. { DDRC_ZQCTL0(0), 0x03200018 },
  39. { DDRC_ZQCTL1(0), 0x028061A8 },
  40. { DDRC_ZQCTL2(0), 0x00000000 },
  41. { DDRC_DFITMG0(0), 0x0497820A },
  42. { DDRC_DFITMG1(0), 0x00080303 },
  43. { DDRC_DFIUPD0(0), 0xE0400018 },
  44. { DDRC_DFIUPD1(0), 0x00DF00E4 },
  45. { DDRC_DFIUPD2(0), 0x80000000 },
  46. { DDRC_DFIMISC(0), 0x00000011 },
  47. { DDRC_DFITMG2(0), 0x0000170A },
  48. { DDRC_DBICTL(0), 0x00000001 },
  49. { DDRC_DFIPHYMSTR(0), 0x00000001 },
  50. { DDRC_RANKCTL(0), 0x00000c99 },
  51. { DDRC_DRAMTMG2(0), 0x070E171a },
  52. /* address mapping */
  53. { DDRC_ADDRMAP0(0), 0x00000015 },
  54. { DDRC_ADDRMAP3(0), 0x00000000 },
  55. { DDRC_ADDRMAP4(0), 0x00001F1F },
  56. /* bank interleave */
  57. { DDRC_ADDRMAP1(0), 0x00080808 },
  58. { DDRC_ADDRMAP5(0), 0x07070707 },
  59. { DDRC_ADDRMAP6(0), 0x08080707 },
  60. /* performance setting */
  61. { DDRC_ODTCFG(0), 0x0b060908 },
  62. { DDRC_ODTMAP(0), 0x00000000 },
  63. { DDRC_SCHED(0), 0x29511505 },
  64. { DDRC_SCHED1(0), 0x0000002c },
  65. { DDRC_PERFHPR1(0), 0x5900575b },
  66. /* 150T starve and 0x90 max tran len */
  67. { DDRC_PERFLPR1(0), 0x90000096 },
  68. /* 300T starve and 0x10 max tran len */
  69. { DDRC_PERFWR1(0), 0x1000012c },
  70. { DDRC_DBG0(0), 0x00000016 },
  71. { DDRC_DBG1(0), 0x00000000 },
  72. { DDRC_DBGCMD(0), 0x00000000 },
  73. { DDRC_SWCTL(0), 0x00000001 },
  74. { DDRC_POISONCFG(0), 0x00000011 },
  75. { DDRC_PCCFG(0), 0x00000111 },
  76. { DDRC_PCFGR_0(0), 0x000010f3 },
  77. { DDRC_PCFGW_0(0), 0x000072ff },
  78. { DDRC_PCTRL_0(0), 0x00000001 },
  79. /* disable Read Qos*/
  80. { DDRC_PCFGQOS0_0(0), 0x00000e00 },
  81. { DDRC_PCFGQOS1_0(0), 0x0062ffff },
  82. /* disable Write Qos*/
  83. { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
  84. { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
  85. /* Frequency 1: 400mbps */
  86. { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
  87. { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
  88. { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
  89. { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
  90. { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
  91. { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
  92. { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
  93. { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
  94. { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
  95. { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
  96. { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
  97. { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
  98. { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
  99. { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
  100. { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
  101. { DDRC_FREQ1_INIT3(0), 0x00840000 },
  102. { DDRC_FREQ1_INIT4(0), 0x00310008 },
  103. { DDRC_FREQ1_INIT6(0), 0x0066004a },
  104. { DDRC_FREQ1_INIT7(0), 0x0006004a },
  105. /* Frequency 2: 100mbps */
  106. { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
  107. { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
  108. { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
  109. { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
  110. { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
  111. { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
  112. { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
  113. { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
  114. { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
  115. { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
  116. { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
  117. { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
  118. { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
  119. { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
  120. { DDRC_FREQ2_INIT3(0), 0x00840000 },
  121. { DDRC_FREQ2_INIT4(0), 0x00310008 },
  122. { DDRC_FREQ2_INIT6(0), 0x0066004a },
  123. { DDRC_FREQ2_INIT7(0), 0x0006004a },
  124. };
  125. /* PHY Initialize Configuration */
  126. struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
  127. { 0x20110, 0x02 },
  128. { 0x20111, 0x03 },
  129. { 0x20112, 0x04 },
  130. { 0x20113, 0x05 },
  131. { 0x20114, 0x00 },
  132. { 0x20115, 0x01 },
  133. { 0x1005f, 0x1ff },
  134. { 0x1015f, 0x1ff },
  135. { 0x1105f, 0x1ff },
  136. { 0x1115f, 0x1ff },
  137. { 0x1205f, 0x1ff },
  138. { 0x1215f, 0x1ff },
  139. { 0x1305f, 0x1ff },
  140. { 0x1315f, 0x1ff },
  141. { 0x11005f, 0x1ff },
  142. { 0x11015f, 0x1ff },
  143. { 0x11105f, 0x1ff },
  144. { 0x11115f, 0x1ff },
  145. { 0x11205f, 0x1ff },
  146. { 0x11215f, 0x1ff },
  147. { 0x11305f, 0x1ff },
  148. { 0x11315f, 0x1ff },
  149. { 0x21005f, 0x1ff },
  150. { 0x21015f, 0x1ff },
  151. { 0x21105f, 0x1ff },
  152. { 0x21115f, 0x1ff },
  153. { 0x21205f, 0x1ff },
  154. { 0x21215f, 0x1ff },
  155. { 0x21305f, 0x1ff },
  156. { 0x21315f, 0x1ff },
  157. { 0x55, 0x1ff },
  158. { 0x1055, 0x1ff },
  159. { 0x2055, 0x1ff },
  160. { 0x3055, 0x1ff },
  161. { 0x4055, 0x1ff },
  162. { 0x5055, 0x1ff },
  163. { 0x6055, 0x1ff },
  164. { 0x7055, 0x1ff },
  165. { 0x8055, 0x1ff },
  166. { 0x9055, 0x1ff },
  167. { 0x200c5, 0x19 },
  168. { 0x1200c5, 0x7 },
  169. { 0x2200c5, 0x7 },
  170. { 0x2002e, 0x2 },
  171. { 0x12002e, 0x2 },
  172. { 0x22002e, 0x2 },
  173. { 0x90204, 0x0 },
  174. { 0x190204, 0x0 },
  175. { 0x290204, 0x0 },
  176. #ifdef WR_POST_EXT_3200
  177. { 0x20024, 0xeb },
  178. #else
  179. { 0x20024, 0xab },
  180. #endif
  181. { 0x2003a, 0x0 },
  182. { 0x120024, 0xab },
  183. { 0x2003a, 0x0 },
  184. { 0x220024, 0xab },
  185. { 0x2003a, 0x0 },
  186. { 0x20056, 0x3 },
  187. { 0x120056, 0xa },
  188. { 0x220056, 0xa },
  189. { 0x1004d, 0xe00 },
  190. { 0x1014d, 0xe00 },
  191. { 0x1104d, 0xe00 },
  192. { 0x1114d, 0xe00 },
  193. { 0x1204d, 0xe00 },
  194. { 0x1214d, 0xe00 },
  195. { 0x1304d, 0xe00 },
  196. { 0x1314d, 0xe00 },
  197. { 0x11004d, 0xe00 },
  198. { 0x11014d, 0xe00 },
  199. { 0x11104d, 0xe00 },
  200. { 0x11114d, 0xe00 },
  201. { 0x11204d, 0xe00 },
  202. { 0x11214d, 0xe00 },
  203. { 0x11304d, 0xe00 },
  204. { 0x11314d, 0xe00 },
  205. { 0x21004d, 0xe00 },
  206. { 0x21014d, 0xe00 },
  207. { 0x21104d, 0xe00 },
  208. { 0x21114d, 0xe00 },
  209. { 0x21204d, 0xe00 },
  210. { 0x21214d, 0xe00 },
  211. { 0x21304d, 0xe00 },
  212. { 0x21314d, 0xe00 },
  213. { 0x10049, 0xfbe },
  214. { 0x10149, 0xfbe },
  215. { 0x11049, 0xfbe },
  216. { 0x11149, 0xfbe },
  217. { 0x12049, 0xfbe },
  218. { 0x12149, 0xfbe },
  219. { 0x13049, 0xfbe },
  220. { 0x13149, 0xfbe },
  221. { 0x110049, 0xfbe },
  222. { 0x110149, 0xfbe },
  223. { 0x111049, 0xfbe },
  224. { 0x111149, 0xfbe },
  225. { 0x112049, 0xfbe },
  226. { 0x112149, 0xfbe },
  227. { 0x113049, 0xfbe },
  228. { 0x113149, 0xfbe },
  229. { 0x210049, 0xfbe },
  230. { 0x210149, 0xfbe },
  231. { 0x211049, 0xfbe },
  232. { 0x211149, 0xfbe },
  233. { 0x212049, 0xfbe },
  234. { 0x212149, 0xfbe },
  235. { 0x213049, 0xfbe },
  236. { 0x213149, 0xfbe },
  237. { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  238. { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  239. { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  240. { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  241. { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  242. { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  243. { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  244. { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  245. { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  246. { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  247. { 0x20018, 0x3 },
  248. { 0x20075, 0x4 },
  249. { 0x20050, 0x0 },
  250. { 0x20008, 0x320 },
  251. { 0x120008, 0x64 },
  252. { 0x220008, 0x19 },
  253. { 0x20088, 0x9 },
  254. { 0x200b2, 0x104 },
  255. { 0x10043, 0x5a1 },
  256. { 0x10143, 0x5a1 },
  257. { 0x11043, 0x5a1 },
  258. { 0x11143, 0x5a1 },
  259. { 0x12043, 0x5a1 },
  260. { 0x12143, 0x5a1 },
  261. { 0x13043, 0x5a1 },
  262. { 0x13143, 0x5a1 },
  263. { 0x1200b2, 0x104 },
  264. { 0x110043, 0x5a1 },
  265. { 0x110143, 0x5a1 },
  266. { 0x111043, 0x5a1 },
  267. { 0x111143, 0x5a1 },
  268. { 0x112043, 0x5a1 },
  269. { 0x112143, 0x5a1 },
  270. { 0x113043, 0x5a1 },
  271. { 0x113143, 0x5a1 },
  272. { 0x2200b2, 0x104 },
  273. { 0x210043, 0x5a1 },
  274. { 0x210143, 0x5a1 },
  275. { 0x211043, 0x5a1 },
  276. { 0x211143, 0x5a1 },
  277. { 0x212043, 0x5a1 },
  278. { 0x212143, 0x5a1 },
  279. { 0x213043, 0x5a1 },
  280. { 0x213143, 0x5a1 },
  281. { 0x200fa, 0x1 },
  282. { 0x1200fa, 0x1 },
  283. { 0x2200fa, 0x1 },
  284. { 0x20019, 0x1 },
  285. { 0x120019, 0x1 },
  286. { 0x220019, 0x1 },
  287. { 0x200f0, 0x660 },
  288. { 0x200f1, 0x0 },
  289. { 0x200f2, 0x4444 },
  290. { 0x200f3, 0x8888 },
  291. { 0x200f4, 0x5665 },
  292. { 0x200f5, 0x0 },
  293. { 0x200f6, 0x0 },
  294. { 0x200f7, 0xf000 },
  295. { 0x20025, 0x0 },
  296. { 0x2002d, 0x0 },
  297. { 0x12002d, 0x0 },
  298. { 0x22002d, 0x0 },
  299. { 0x200c7, 0x80 },
  300. { 0x1200c7, 0x80 },
  301. { 0x2200c7, 0x80 },
  302. { 0x200ca, 0x106 },
  303. { 0x1200ca, 0x106 },
  304. { 0x2200ca, 0x106 },
  305. };
  306. /* P0 message block paremeter for training firmware */
  307. struct dram_cfg_param lpddr4_fsp0_cfg[] = {
  308. { 0xd0000, 0x0 },
  309. { 0x54000, 0x0 },
  310. { 0x54001, 0x0 },
  311. { 0x54002, 0x0 },
  312. { 0x54003, 0xc80 },
  313. { 0x54004, 0x2 },
  314. { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
  315. { 0x54006, LPDDR4_PHY_VREF_VALUE },
  316. { 0x54007, 0x0 },
  317. { 0x54008, 0x131f },
  318. { 0x54009, LPDDR4_HDT_CTL_3200_1D },
  319. { 0x5400a, 0x0 },
  320. { 0x5400b, 0x2 },
  321. { 0x5400c, 0x0 },
  322. { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
  323. { 0x5400e, 0x0 },
  324. { 0x5400f, 0x0 },
  325. { 0x54010, 0x0 },
  326. { 0x54011, 0x0 },
  327. { 0x54012, 0x310 },
  328. { 0x54013, 0x0 },
  329. { 0x54014, 0x0 },
  330. { 0x54015, 0x0 },
  331. { 0x54016, 0x0 },
  332. { 0x54017, 0x0 },
  333. { 0x54018, 0x0 },
  334. { 0x54019, 0x2dd4 },
  335. #ifdef WR_POST_EXT_3200
  336. { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
  337. #else
  338. { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
  339. #endif
  340. { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
  341. (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
  342. { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  343. { 0x5401d, 0x0 },
  344. { 0x5401e, LPDDR4_MR22_RANK0 },
  345. { 0x5401f, 0x2dd4 },
  346. #ifdef WR_POST_EXT_3200
  347. { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
  348. #else
  349. { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
  350. #endif
  351. { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
  352. (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
  353. { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  354. { 0x54023, 0x0 },
  355. { 0x54024, LPDDR4_MR22_RANK1 },
  356. { 0x54025, 0x0 },
  357. { 0x54026, 0x0 },
  358. { 0x54027, 0x0 },
  359. { 0x54028, 0x0 },
  360. { 0x54029, 0x0 },
  361. { 0x5402a, 0x0 },
  362. { 0x5402b, 0x1000 },
  363. { 0x5402c, 0x3 },
  364. { 0x5402d, 0x0 },
  365. { 0x5402e, 0x0 },
  366. { 0x5402f, 0x0 },
  367. { 0x54030, 0x0 },
  368. { 0x54031, 0x0 },
  369. { 0x54032, 0xd400 },
  370. /* MR3/MR2 */
  371. #ifdef WR_POST_EXT_3200
  372. { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
  373. #else
  374. { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
  375. #endif
  376. /* MR11/MR4 */
  377. { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
  378. /* self:0x284d//MR13/MR12 */
  379. { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
  380. /* MR16/MR14*/
  381. { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
  382. { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
  383. /* MR1 */
  384. { 0x54038, 0xd400 },
  385. /* MR3/MR2 */
  386. #ifdef WR_POST_EXT_3200
  387. { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
  388. #else
  389. { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
  390. #endif
  391. /* MR11/MR4 */
  392. { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
  393. /* self:0x284d//MR13/MR12 */
  394. { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
  395. /* MR16/MR14 */
  396. { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
  397. { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
  398. /* { 0x5403d, 0x500 } */
  399. { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
  400. { 0x5403e, 0x0 },
  401. { 0x5403f, 0x0 },
  402. { 0x54040, 0x0 },
  403. { 0x54041, 0x0 },
  404. { 0x54042, 0x0 },
  405. { 0x54043, 0x0 },
  406. { 0x54044, 0x0 },
  407. { 0xd0000, 0x1 },
  408. };
  409. /* P1 message block paremeter for training firmware */
  410. struct dram_cfg_param lpddr4_fsp1_cfg[] = {
  411. { 0xd0000, 0x0 },
  412. { 0x54000, 0x0 },
  413. { 0x54001, 0x0 },
  414. { 0x54002, 0x101 },
  415. { 0x54003, 0x190 },
  416. { 0x54004, 0x2 },
  417. /* PHY Ron/Rtt */
  418. { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
  419. { 0x54006, LPDDR4_PHY_VREF_VALUE },
  420. { 0x54007, 0x0 },
  421. { 0x54008, LPDDR4_TRAIN_SEQ_400 },
  422. { 0x54009, LPDDR4_HDT_CTL_400_1D },
  423. { 0x5400a, 0x0 },
  424. { 0x5400b, 0x2 },
  425. { 0x5400c, 0x0 },
  426. { 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
  427. { 0x5400e, 0x0 },
  428. { 0x5400f, 0x0 },
  429. { 0x54010, 0x0 },
  430. { 0x54011, 0x0 },
  431. { 0x54012, 0x310 },
  432. { 0x54013, 0x0 },
  433. { 0x54014, 0x0 },
  434. { 0x54015, 0x0 },
  435. { 0x54016, 0x0 },
  436. { 0x54017, 0x0 },
  437. { 0x54018, 0x0 },
  438. { 0x54019, 0x84 },
  439. /* MR4/MR3 */
  440. { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
  441. /* MR12/MR11 */
  442. { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  443. LPDDR4_RTT_DQ)/*0x4d46*/ },
  444. /* self:0x4d28//MR14/MR13 */
  445. { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
  446. { 0x5401d, 0x0 },
  447. { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
  448. { 0x5401f, 0x84 },
  449. { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
  450. { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  451. LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
  452. /* self:0x4d28//MR14/MR13 */
  453. { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
  454. { 0x54023, 0x0 },
  455. { 0x54024, LPDDR4_MR22_RANK1 },
  456. { 0x54025, 0x0 },
  457. { 0x54026, 0x0 },
  458. { 0x54027, 0x0 },
  459. { 0x54028, 0x0 },
  460. { 0x54029, 0x0 },
  461. { 0x5402a, 0x0 },
  462. { 0x5402b, 0x1000 },
  463. { 0x5402c, 0x3 },
  464. { 0x5402d, 0x0 },
  465. { 0x5402e, 0x0 },
  466. { 0x5402f, 0x0 },
  467. { 0x54030, 0x0 },
  468. { 0x54031, 0x0 },
  469. { 0x54032, 0x8400 },
  470. { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  471. { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  472. { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  473. { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  474. { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  475. { 0x54038, 0x8400 },
  476. { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  477. { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  478. { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  479. { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  480. { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  481. { 0x5403e, 0x0 },
  482. { 0x5403f, 0x0 },
  483. { 0x54040, 0x0 },
  484. { 0x54041, 0x0 },
  485. { 0x54042, 0x0 },
  486. { 0x54043, 0x0 },
  487. { 0x54044, 0x0 },
  488. { 0xd0000, 0x1 },
  489. };
  490. /* P2 message block paremeter for training firmware */
  491. struct dram_cfg_param lpddr4_fsp2_cfg[] = {
  492. { 0xd0000, 0x0 },
  493. { 0x54000, 0x0 },
  494. { 0x54001, 0x0 },
  495. { 0x54002, 0x102 },
  496. { 0x54003, 0x64 },
  497. { 0x54004, 0x2 },
  498. { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
  499. { 0x54006, LPDDR4_PHY_VREF_VALUE },
  500. { 0x54007, 0x0 },
  501. { 0x54008, LPDDR4_TRAIN_SEQ_100 },
  502. { 0x54009, LPDDR4_HDT_CTL_100_1D },
  503. { 0x5400a, 0x0 },
  504. { 0x5400b, 0x2 },
  505. { 0x5400c, 0x0 },
  506. { 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
  507. { 0x5400e, 0x0 },
  508. { 0x5400f, 0x0 },
  509. { 0x54010, 0x0 },
  510. { 0x54011, 0x0 },
  511. { 0x54012, 0x310 },
  512. { 0x54013, 0x0 },
  513. { 0x54014, 0x0 },
  514. { 0x54015, 0x0 },
  515. { 0x54016, 0x0 },
  516. { 0x54017, 0x0 },
  517. { 0x54018, 0x0 },
  518. { 0x54019, 0x84 },
  519. { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
  520. { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  521. LPDDR4_RTT_DQ) },
  522. { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  523. { 0x5401d, 0x0 },
  524. { 0x5401e, LPDDR4_MR22_RANK0 },
  525. { 0x5401f, 0x84 },
  526. { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
  527. { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  528. LPDDR4_RTT_DQ) },
  529. { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  530. { 0x54023, 0x0 },
  531. { 0x54024, LPDDR4_MR22_RANK1 },
  532. { 0x54025, 0x0 },
  533. { 0x54026, 0x0 },
  534. { 0x54027, 0x0 },
  535. { 0x54028, 0x0 },
  536. { 0x54029, 0x0 },
  537. { 0x5402a, 0x0 },
  538. { 0x5402b, 0x1000 },
  539. { 0x5402c, 0x3 },
  540. { 0x5402d, 0x0 },
  541. { 0x5402e, 0x0 },
  542. { 0x5402f, 0x0 },
  543. { 0x54030, 0x0 },
  544. { 0x54031, 0x0 },
  545. { 0x54032, 0x8400 },
  546. { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  547. { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  548. { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  549. { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  550. { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  551. { 0x54038, 0x8400 },
  552. { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  553. { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  554. { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  555. { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  556. { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  557. { 0x5403e, 0x0 },
  558. { 0x5403f, 0x0 },
  559. { 0x54040, 0x0 },
  560. { 0x54041, 0x0 },
  561. { 0x54042, 0x0 },
  562. { 0x54043, 0x0 },
  563. { 0x54044, 0x0 },
  564. { 0xd0000, 0x1 },
  565. };
  566. /* P0 2D message block paremeter for training firmware */
  567. struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
  568. { 0xd0000, 0x0 },
  569. { 0x54000, 0x0 },
  570. { 0x54001, 0x0 },
  571. { 0x54002, 0x0 },
  572. { 0x54003, 0xc80 },
  573. { 0x54004, 0x2 },
  574. { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
  575. { 0x54006, LPDDR4_PHY_VREF_VALUE },
  576. { 0x54007, 0x0 },
  577. { 0x54008, 0x61 },
  578. { 0x54009, LPDDR4_HDT_CTL_2D },
  579. { 0x5400a, 0x0 },
  580. { 0x5400b, 0x2 },
  581. { 0x5400c, 0x0 },
  582. { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
  583. { 0x5400e, 0x0 },
  584. { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
  585. { 0x54010, LPDDR4_2D_WEIGHT },
  586. { 0x54011, 0x0 },
  587. { 0x54012, 0x310 },
  588. { 0x54013, 0x0 },
  589. { 0x54014, 0x0 },
  590. { 0x54015, 0x0 },
  591. { 0x54016, 0x0 },
  592. { 0x54017, 0x0 },
  593. { 0x54018, 0x0 },
  594. { 0x54019, 0x2dd4 },
  595. #ifdef WR_POST_EXT_3200
  596. { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
  597. #else
  598. { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
  599. #endif
  600. { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
  601. (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
  602. { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  603. { 0x5401d, 0x0 },
  604. { 0x5401e, LPDDR4_MR22_RANK0 },
  605. { 0x5401f, 0x2dd4 },
  606. #ifdef WR_POST_EXT_3200
  607. { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
  608. #else
  609. { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
  610. #endif
  611. { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
  612. (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
  613. { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  614. { 0x54023, 0x0 },
  615. { 0x54024, LPDDR4_MR22_RANK1 },
  616. { 0x54025, 0x0 },
  617. { 0x54026, 0x0 },
  618. { 0x54027, 0x0 },
  619. { 0x54028, 0x0 },
  620. { 0x54029, 0x0 },
  621. { 0x5402a, 0x0 },
  622. { 0x5402b, 0x1000 },
  623. { 0x5402c, 0x3 },
  624. { 0x5402d, 0x0 },
  625. { 0x5402e, 0x0 },
  626. { 0x5402f, 0x0 },
  627. { 0x54030, 0x0 },
  628. { 0x54031, 0x0 },
  629. { 0x54032, 0xd400 },
  630. #ifdef WR_POST_EXT_3200
  631. { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  632. #else
  633. { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
  634. #endif
  635. { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
  636. { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  637. { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  638. { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  639. { 0x54038, 0xd400 },
  640. #ifdef WR_POST_EXT_3200
  641. { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  642. #else
  643. { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
  644. #endif
  645. { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
  646. { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  647. { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  648. { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  649. { 0x5403e, 0x0 },
  650. { 0x5403f, 0x0 },
  651. { 0x54040, 0x0 },
  652. { 0x54041, 0x0 },
  653. { 0x54042, 0x0 },
  654. { 0x54043, 0x0 },
  655. { 0x54044, 0x0 },
  656. { 0xd0000, 0x1 },
  657. };
  658. /* DRAM PHY init engine image */
  659. struct dram_cfg_param lpddr4_phy_pie[] = {
  660. { 0xd0000, 0x0 },
  661. { 0x90000, 0x10 },
  662. { 0x90001, 0x400 },
  663. { 0x90002, 0x10e },
  664. { 0x90003, 0x0 },
  665. { 0x90004, 0x0 },
  666. { 0x90005, 0x8 },
  667. { 0x90029, 0xb },
  668. { 0x9002a, 0x480 },
  669. { 0x9002b, 0x109 },
  670. { 0x9002c, 0x8 },
  671. { 0x9002d, 0x448 },
  672. { 0x9002e, 0x139 },
  673. { 0x9002f, 0x8 },
  674. { 0x90030, 0x478 },
  675. { 0x90031, 0x109 },
  676. { 0x90032, 0x0 },
  677. { 0x90033, 0xe8 },
  678. { 0x90034, 0x109 },
  679. { 0x90035, 0x2 },
  680. { 0x90036, 0x10 },
  681. { 0x90037, 0x139 },
  682. { 0x90038, 0xf },
  683. { 0x90039, 0x7c0 },
  684. { 0x9003a, 0x139 },
  685. { 0x9003b, 0x44 },
  686. { 0x9003c, 0x630 },
  687. { 0x9003d, 0x159 },
  688. { 0x9003e, 0x14f },
  689. { 0x9003f, 0x630 },
  690. { 0x90040, 0x159 },
  691. { 0x90041, 0x47 },
  692. { 0x90042, 0x630 },
  693. { 0x90043, 0x149 },
  694. { 0x90044, 0x4f },
  695. { 0x90045, 0x630 },
  696. { 0x90046, 0x179 },
  697. { 0x90047, 0x8 },
  698. { 0x90048, 0xe0 },
  699. { 0x90049, 0x109 },
  700. { 0x9004a, 0x0 },
  701. { 0x9004b, 0x7c8 },
  702. { 0x9004c, 0x109 },
  703. { 0x9004d, 0x0 },
  704. { 0x9004e, 0x1 },
  705. { 0x9004f, 0x8 },
  706. { 0x90050, 0x0 },
  707. { 0x90051, 0x45a },
  708. { 0x90052, 0x9 },
  709. { 0x90053, 0x0 },
  710. { 0x90054, 0x448 },
  711. { 0x90055, 0x109 },
  712. { 0x90056, 0x40 },
  713. { 0x90057, 0x630 },
  714. { 0x90058, 0x179 },
  715. { 0x90059, 0x1 },
  716. { 0x9005a, 0x618 },
  717. { 0x9005b, 0x109 },
  718. { 0x9005c, 0x40c0 },
  719. { 0x9005d, 0x630 },
  720. { 0x9005e, 0x149 },
  721. { 0x9005f, 0x8 },
  722. { 0x90060, 0x4 },
  723. { 0x90061, 0x48 },
  724. { 0x90062, 0x4040 },
  725. { 0x90063, 0x630 },
  726. { 0x90064, 0x149 },
  727. { 0x90065, 0x0 },
  728. { 0x90066, 0x4 },
  729. { 0x90067, 0x48 },
  730. { 0x90068, 0x40 },
  731. { 0x90069, 0x630 },
  732. { 0x9006a, 0x149 },
  733. { 0x9006b, 0x10 },
  734. { 0x9006c, 0x4 },
  735. { 0x9006d, 0x18 },
  736. { 0x9006e, 0x0 },
  737. { 0x9006f, 0x4 },
  738. { 0x90070, 0x78 },
  739. { 0x90071, 0x549 },
  740. { 0x90072, 0x630 },
  741. { 0x90073, 0x159 },
  742. { 0x90074, 0xd49 },
  743. { 0x90075, 0x630 },
  744. { 0x90076, 0x159 },
  745. { 0x90077, 0x94a },
  746. { 0x90078, 0x630 },
  747. { 0x90079, 0x159 },
  748. { 0x9007a, 0x441 },
  749. { 0x9007b, 0x630 },
  750. { 0x9007c, 0x149 },
  751. { 0x9007d, 0x42 },
  752. { 0x9007e, 0x630 },
  753. { 0x9007f, 0x149 },
  754. { 0x90080, 0x1 },
  755. { 0x90081, 0x630 },
  756. { 0x90082, 0x149 },
  757. { 0x90083, 0x0 },
  758. { 0x90084, 0xe0 },
  759. { 0x90085, 0x109 },
  760. { 0x90086, 0xa },
  761. { 0x90087, 0x10 },
  762. { 0x90088, 0x109 },
  763. { 0x90089, 0x9 },
  764. { 0x9008a, 0x3c0 },
  765. { 0x9008b, 0x149 },
  766. { 0x9008c, 0x9 },
  767. { 0x9008d, 0x3c0 },
  768. { 0x9008e, 0x159 },
  769. { 0x9008f, 0x18 },
  770. { 0x90090, 0x10 },
  771. { 0x90091, 0x109 },
  772. { 0x90092, 0x0 },
  773. { 0x90093, 0x3c0 },
  774. { 0x90094, 0x109 },
  775. { 0x90095, 0x18 },
  776. { 0x90096, 0x4 },
  777. { 0x90097, 0x48 },
  778. { 0x90098, 0x18 },
  779. { 0x90099, 0x4 },
  780. { 0x9009a, 0x58 },
  781. { 0x9009b, 0xa },
  782. { 0x9009c, 0x10 },
  783. { 0x9009d, 0x109 },
  784. { 0x9009e, 0x2 },
  785. { 0x9009f, 0x10 },
  786. { 0x900a0, 0x109 },
  787. { 0x900a1, 0x5 },
  788. { 0x900a2, 0x7c0 },
  789. { 0x900a3, 0x109 },
  790. { 0x900a4, 0x10 },
  791. { 0x900a5, 0x10 },
  792. { 0x900a6, 0x109 },
  793. { 0x40000, 0x811 },
  794. { 0x40020, 0x880 },
  795. { 0x40040, 0x0 },
  796. { 0x40060, 0x0 },
  797. { 0x40001, 0x4008 },
  798. { 0x40021, 0x83 },
  799. { 0x40041, 0x4f },
  800. { 0x40061, 0x0 },
  801. { 0x40002, 0x4040 },
  802. { 0x40022, 0x83 },
  803. { 0x40042, 0x51 },
  804. { 0x40062, 0x0 },
  805. { 0x40003, 0x811 },
  806. { 0x40023, 0x880 },
  807. { 0x40043, 0x0 },
  808. { 0x40063, 0x0 },
  809. { 0x40004, 0x720 },
  810. { 0x40024, 0xf },
  811. { 0x40044, 0x1740 },
  812. { 0x40064, 0x0 },
  813. { 0x40005, 0x16 },
  814. { 0x40025, 0x83 },
  815. { 0x40045, 0x4b },
  816. { 0x40065, 0x0 },
  817. { 0x40006, 0x716 },
  818. { 0x40026, 0xf },
  819. { 0x40046, 0x2001 },
  820. { 0x40066, 0x0 },
  821. { 0x40007, 0x716 },
  822. { 0x40027, 0xf },
  823. { 0x40047, 0x2800 },
  824. { 0x40067, 0x0 },
  825. { 0x40008, 0x716 },
  826. { 0x40028, 0xf },
  827. { 0x40048, 0xf00 },
  828. { 0x40068, 0x0 },
  829. { 0x40009, 0x720 },
  830. { 0x40029, 0xf },
  831. { 0x40049, 0x1400 },
  832. { 0x40069, 0x0 },
  833. { 0x4000a, 0xe08 },
  834. { 0x4002a, 0xc15 },
  835. { 0x4004a, 0x0 },
  836. { 0x4006a, 0x0 },
  837. { 0x4000b, 0x623 },
  838. { 0x4002b, 0x15 },
  839. { 0x4004b, 0x0 },
  840. { 0x4006b, 0x0 },
  841. { 0x4000c, 0x4028 },
  842. { 0x4002c, 0x80 },
  843. { 0x4004c, 0x0 },
  844. { 0x4006c, 0x0 },
  845. { 0x4000d, 0xe08 },
  846. { 0x4002d, 0xc1a },
  847. { 0x4004d, 0x0 },
  848. { 0x4006d, 0x0 },
  849. { 0x4000e, 0x623 },
  850. { 0x4002e, 0x1a },
  851. { 0x4004e, 0x0 },
  852. { 0x4006e, 0x0 },
  853. { 0x4000f, 0x4040 },
  854. { 0x4002f, 0x80 },
  855. { 0x4004f, 0x0 },
  856. { 0x4006f, 0x0 },
  857. { 0x40010, 0x2604 },
  858. { 0x40030, 0x15 },
  859. { 0x40050, 0x0 },
  860. { 0x40070, 0x0 },
  861. { 0x40011, 0x708 },
  862. { 0x40031, 0x5 },
  863. { 0x40051, 0x0 },
  864. { 0x40071, 0x2002 },
  865. { 0x40012, 0x8 },
  866. { 0x40032, 0x80 },
  867. { 0x40052, 0x0 },
  868. { 0x40072, 0x0 },
  869. { 0x40013, 0x2604 },
  870. { 0x40033, 0x1a },
  871. { 0x40053, 0x0 },
  872. { 0x40073, 0x0 },
  873. { 0x40014, 0x708 },
  874. { 0x40034, 0xa },
  875. { 0x40054, 0x0 },
  876. { 0x40074, 0x2002 },
  877. { 0x40015, 0x4040 },
  878. { 0x40035, 0x80 },
  879. { 0x40055, 0x0 },
  880. { 0x40075, 0x0 },
  881. { 0x40016, 0x60a },
  882. { 0x40036, 0x15 },
  883. { 0x40056, 0x1200 },
  884. { 0x40076, 0x0 },
  885. { 0x40017, 0x61a },
  886. { 0x40037, 0x15 },
  887. { 0x40057, 0x1300 },
  888. { 0x40077, 0x0 },
  889. { 0x40018, 0x60a },
  890. { 0x40038, 0x1a },
  891. { 0x40058, 0x1200 },
  892. { 0x40078, 0x0 },
  893. { 0x40019, 0x642 },
  894. { 0x40039, 0x1a },
  895. { 0x40059, 0x1300 },
  896. { 0x40079, 0x0 },
  897. { 0x4001a, 0x4808 },
  898. { 0x4003a, 0x880 },
  899. { 0x4005a, 0x0 },
  900. { 0x4007a, 0x0 },
  901. { 0x900a7, 0x0 },
  902. { 0x900a8, 0x790 },
  903. { 0x900a9, 0x11a },
  904. { 0x900aa, 0x8 },
  905. { 0x900ab, 0x7aa },
  906. { 0x900ac, 0x2a },
  907. { 0x900ad, 0x10 },
  908. { 0x900ae, 0x7b2 },
  909. { 0x900af, 0x2a },
  910. { 0x900b0, 0x0 },
  911. { 0x900b1, 0x7c8 },
  912. { 0x900b2, 0x109 },
  913. { 0x900b3, 0x10 },
  914. { 0x900b4, 0x2a8 },
  915. { 0x900b5, 0x129 },
  916. { 0x900b6, 0x8 },
  917. { 0x900b7, 0x370 },
  918. { 0x900b8, 0x129 },
  919. { 0x900b9, 0xa },
  920. { 0x900ba, 0x3c8 },
  921. { 0x900bb, 0x1a9 },
  922. { 0x900bc, 0xc },
  923. { 0x900bd, 0x408 },
  924. { 0x900be, 0x199 },
  925. { 0x900bf, 0x14 },
  926. { 0x900c0, 0x790 },
  927. { 0x900c1, 0x11a },
  928. { 0x900c2, 0x8 },
  929. { 0x900c3, 0x4 },
  930. { 0x900c4, 0x18 },
  931. { 0x900c5, 0xe },
  932. { 0x900c6, 0x408 },
  933. { 0x900c7, 0x199 },
  934. { 0x900c8, 0x8 },
  935. { 0x900c9, 0x8568 },
  936. { 0x900ca, 0x108 },
  937. { 0x900cb, 0x18 },
  938. { 0x900cc, 0x790 },
  939. { 0x900cd, 0x16a },
  940. { 0x900ce, 0x8 },
  941. { 0x900cf, 0x1d8 },
  942. { 0x900d0, 0x169 },
  943. { 0x900d1, 0x10 },
  944. { 0x900d2, 0x8558 },
  945. { 0x900d3, 0x168 },
  946. { 0x900d4, 0x70 },
  947. { 0x900d5, 0x788 },
  948. { 0x900d6, 0x16a },
  949. { 0x900d7, 0x1ff8 },
  950. { 0x900d8, 0x85a8 },
  951. { 0x900d9, 0x1e8 },
  952. { 0x900da, 0x50 },
  953. { 0x900db, 0x798 },
  954. { 0x900dc, 0x16a },
  955. { 0x900dd, 0x60 },
  956. { 0x900de, 0x7a0 },
  957. { 0x900df, 0x16a },
  958. { 0x900e0, 0x8 },
  959. { 0x900e1, 0x8310 },
  960. { 0x900e2, 0x168 },
  961. { 0x900e3, 0x8 },
  962. { 0x900e4, 0xa310 },
  963. { 0x900e5, 0x168 },
  964. { 0x900e6, 0xa },
  965. { 0x900e7, 0x408 },
  966. { 0x900e8, 0x169 },
  967. { 0x900e9, 0x6e },
  968. { 0x900ea, 0x0 },
  969. { 0x900eb, 0x68 },
  970. { 0x900ec, 0x0 },
  971. { 0x900ed, 0x408 },
  972. { 0x900ee, 0x169 },
  973. { 0x900ef, 0x0 },
  974. { 0x900f0, 0x8310 },
  975. { 0x900f1, 0x168 },
  976. { 0x900f2, 0x0 },
  977. { 0x900f3, 0xa310 },
  978. { 0x900f4, 0x168 },
  979. { 0x900f5, 0x1ff8 },
  980. { 0x900f6, 0x85a8 },
  981. { 0x900f7, 0x1e8 },
  982. { 0x900f8, 0x68 },
  983. { 0x900f9, 0x798 },
  984. { 0x900fa, 0x16a },
  985. { 0x900fb, 0x78 },
  986. { 0x900fc, 0x7a0 },
  987. { 0x900fd, 0x16a },
  988. { 0x900fe, 0x68 },
  989. { 0x900ff, 0x790 },
  990. { 0x90100, 0x16a },
  991. { 0x90101, 0x8 },
  992. { 0x90102, 0x8b10 },
  993. { 0x90103, 0x168 },
  994. { 0x90104, 0x8 },
  995. { 0x90105, 0xab10 },
  996. { 0x90106, 0x168 },
  997. { 0x90107, 0xa },
  998. { 0x90108, 0x408 },
  999. { 0x90109, 0x169 },
  1000. { 0x9010a, 0x58 },
  1001. { 0x9010b, 0x0 },
  1002. { 0x9010c, 0x68 },
  1003. { 0x9010d, 0x0 },
  1004. { 0x9010e, 0x408 },
  1005. { 0x9010f, 0x169 },
  1006. { 0x90110, 0x0 },
  1007. { 0x90111, 0x8b10 },
  1008. { 0x90112, 0x168 },
  1009. { 0x90113, 0x0 },
  1010. { 0x90114, 0xab10 },
  1011. { 0x90115, 0x168 },
  1012. { 0x90116, 0x0 },
  1013. { 0x90117, 0x1d8 },
  1014. { 0x90118, 0x169 },
  1015. { 0x90119, 0x80 },
  1016. { 0x9011a, 0x790 },
  1017. { 0x9011b, 0x16a },
  1018. { 0x9011c, 0x18 },
  1019. { 0x9011d, 0x7aa },
  1020. { 0x9011e, 0x6a },
  1021. { 0x9011f, 0xa },
  1022. { 0x90120, 0x0 },
  1023. { 0x90121, 0x1e9 },
  1024. { 0x90122, 0x8 },
  1025. { 0x90123, 0x8080 },
  1026. { 0x90124, 0x108 },
  1027. { 0x90125, 0xf },
  1028. { 0x90126, 0x408 },
  1029. { 0x90127, 0x169 },
  1030. { 0x90128, 0xc },
  1031. { 0x90129, 0x0 },
  1032. { 0x9012a, 0x68 },
  1033. { 0x9012b, 0x9 },
  1034. { 0x9012c, 0x0 },
  1035. { 0x9012d, 0x1a9 },
  1036. { 0x9012e, 0x0 },
  1037. { 0x9012f, 0x408 },
  1038. { 0x90130, 0x169 },
  1039. { 0x90131, 0x0 },
  1040. { 0x90132, 0x8080 },
  1041. { 0x90133, 0x108 },
  1042. { 0x90134, 0x8 },
  1043. { 0x90135, 0x7aa },
  1044. { 0x90136, 0x6a },
  1045. { 0x90137, 0x0 },
  1046. { 0x90138, 0x8568 },
  1047. { 0x90139, 0x108 },
  1048. { 0x9013a, 0xb7 },
  1049. { 0x9013b, 0x790 },
  1050. { 0x9013c, 0x16a },
  1051. { 0x9013d, 0x1f },
  1052. { 0x9013e, 0x0 },
  1053. { 0x9013f, 0x68 },
  1054. { 0x90140, 0x8 },
  1055. { 0x90141, 0x8558 },
  1056. { 0x90142, 0x168 },
  1057. { 0x90143, 0xf },
  1058. { 0x90144, 0x408 },
  1059. { 0x90145, 0x169 },
  1060. { 0x90146, 0xc },
  1061. { 0x90147, 0x0 },
  1062. { 0x90148, 0x68 },
  1063. { 0x90149, 0x0 },
  1064. { 0x9014a, 0x408 },
  1065. { 0x9014b, 0x169 },
  1066. { 0x9014c, 0x0 },
  1067. { 0x9014d, 0x8558 },
  1068. { 0x9014e, 0x168 },
  1069. { 0x9014f, 0x8 },
  1070. { 0x90150, 0x3c8 },
  1071. { 0x90151, 0x1a9 },
  1072. { 0x90152, 0x3 },
  1073. { 0x90153, 0x370 },
  1074. { 0x90154, 0x129 },
  1075. { 0x90155, 0x20 },
  1076. { 0x90156, 0x2aa },
  1077. { 0x90157, 0x9 },
  1078. { 0x90158, 0x0 },
  1079. { 0x90159, 0x400 },
  1080. { 0x9015a, 0x10e },
  1081. { 0x9015b, 0x8 },
  1082. { 0x9015c, 0xe8 },
  1083. { 0x9015d, 0x109 },
  1084. { 0x9015e, 0x0 },
  1085. { 0x9015f, 0x8140 },
  1086. { 0x90160, 0x10c },
  1087. { 0x90161, 0x10 },
  1088. { 0x90162, 0x8138 },
  1089. { 0x90163, 0x10c },
  1090. { 0x90164, 0x8 },
  1091. { 0x90165, 0x7c8 },
  1092. { 0x90166, 0x101 },
  1093. { 0x90167, 0x8 },
  1094. { 0x90168, 0x0 },
  1095. { 0x90169, 0x8 },
  1096. { 0x9016a, 0x8 },
  1097. { 0x9016b, 0x448 },
  1098. { 0x9016c, 0x109 },
  1099. { 0x9016d, 0xf },
  1100. { 0x9016e, 0x7c0 },
  1101. { 0x9016f, 0x109 },
  1102. { 0x90170, 0x0 },
  1103. { 0x90171, 0xe8 },
  1104. { 0x90172, 0x109 },
  1105. { 0x90173, 0x47 },
  1106. { 0x90174, 0x630 },
  1107. { 0x90175, 0x109 },
  1108. { 0x90176, 0x8 },
  1109. { 0x90177, 0x618 },
  1110. { 0x90178, 0x109 },
  1111. { 0x90179, 0x8 },
  1112. { 0x9017a, 0xe0 },
  1113. { 0x9017b, 0x109 },
  1114. { 0x9017c, 0x0 },
  1115. { 0x9017d, 0x7c8 },
  1116. { 0x9017e, 0x109 },
  1117. { 0x9017f, 0x8 },
  1118. { 0x90180, 0x8140 },
  1119. { 0x90181, 0x10c },
  1120. { 0x90182, 0x0 },
  1121. { 0x90183, 0x1 },
  1122. { 0x90184, 0x8 },
  1123. { 0x90185, 0x8 },
  1124. { 0x90186, 0x4 },
  1125. { 0x90187, 0x8 },
  1126. { 0x90188, 0x8 },
  1127. { 0x90189, 0x7c8 },
  1128. { 0x9018a, 0x101 },
  1129. { 0x90006, 0x0 },
  1130. { 0x90007, 0x0 },
  1131. { 0x90008, 0x8 },
  1132. { 0x90009, 0x0 },
  1133. { 0x9000a, 0x0 },
  1134. { 0x9000b, 0x0 },
  1135. { 0xd00e7, 0x400 },
  1136. { 0x90017, 0x0 },
  1137. { 0x9001f, 0x2a },
  1138. { 0x90026, 0x6a },
  1139. { 0x400d0, 0x0 },
  1140. { 0x400d1, 0x101 },
  1141. { 0x400d2, 0x105 },
  1142. { 0x400d3, 0x107 },
  1143. { 0x400d4, 0x10f },
  1144. { 0x400d5, 0x202 },
  1145. { 0x400d6, 0x20a },
  1146. { 0x400d7, 0x20b },
  1147. { 0x2003a, 0x2 },
  1148. { 0x2000b, 0x64 },
  1149. { 0x2000c, 0xc8 },
  1150. { 0x2000d, 0x7d0 },
  1151. { 0x2000e, 0x2c },
  1152. { 0x12000b, 0xc },
  1153. { 0x12000c, 0x19 },
  1154. { 0x12000d, 0xfa },
  1155. { 0x12000e, 0x10 },
  1156. { 0x22000b, 0x3 },
  1157. { 0x22000c, 0x6 },
  1158. { 0x22000d, 0x3e },
  1159. { 0x22000e, 0x10 },
  1160. { 0x9000c, 0x0 },
  1161. { 0x9000d, 0x173 },
  1162. { 0x9000e, 0x60 },
  1163. { 0x9000f, 0x6110 },
  1164. { 0x90010, 0x2152 },
  1165. { 0x90011, 0xdfbd },
  1166. { 0x90012, 0x60 },
  1167. { 0x90013, 0x6152 },
  1168. { 0x20010, 0x5a },
  1169. { 0x20011, 0x3 },
  1170. { 0x40080, 0xe0 },
  1171. { 0x40081, 0x12 },
  1172. { 0x40082, 0xe0 },
  1173. { 0x40083, 0x12 },
  1174. { 0x40084, 0xe0 },
  1175. { 0x40085, 0x12 },
  1176. { 0x140080, 0xe0 },
  1177. { 0x140081, 0x12 },
  1178. { 0x140082, 0xe0 },
  1179. { 0x140083, 0x12 },
  1180. { 0x140084, 0xe0 },
  1181. { 0x140085, 0x12 },
  1182. { 0x240080, 0xe0 },
  1183. { 0x240081, 0x12 },
  1184. { 0x240082, 0xe0 },
  1185. { 0x240083, 0x12 },
  1186. { 0x240084, 0xe0 },
  1187. { 0x240085, 0x12 },
  1188. { 0x400fd, 0xf },
  1189. { 0x10011, 0x1 },
  1190. { 0x10012, 0x1 },
  1191. { 0x10013, 0x180 },
  1192. { 0x10018, 0x1 },
  1193. { 0x10002, 0x6209 },
  1194. { 0x100b2, 0x1 },
  1195. { 0x101b4, 0x1 },
  1196. { 0x102b4, 0x1 },
  1197. { 0x103b4, 0x1 },
  1198. { 0x104b4, 0x1 },
  1199. { 0x105b4, 0x1 },
  1200. { 0x106b4, 0x1 },
  1201. { 0x107b4, 0x1 },
  1202. { 0x108b4, 0x1 },
  1203. { 0x11011, 0x1 },
  1204. { 0x11012, 0x1 },
  1205. { 0x11013, 0x180 },
  1206. { 0x11018, 0x1 },
  1207. { 0x11002, 0x6209 },
  1208. { 0x110b2, 0x1 },
  1209. { 0x111b4, 0x1 },
  1210. { 0x112b4, 0x1 },
  1211. { 0x113b4, 0x1 },
  1212. { 0x114b4, 0x1 },
  1213. { 0x115b4, 0x1 },
  1214. { 0x116b4, 0x1 },
  1215. { 0x117b4, 0x1 },
  1216. { 0x118b4, 0x1 },
  1217. { 0x12011, 0x1 },
  1218. { 0x12012, 0x1 },
  1219. { 0x12013, 0x180 },
  1220. { 0x12018, 0x1 },
  1221. { 0x12002, 0x6209 },
  1222. { 0x120b2, 0x1 },
  1223. { 0x121b4, 0x1 },
  1224. { 0x122b4, 0x1 },
  1225. { 0x123b4, 0x1 },
  1226. { 0x124b4, 0x1 },
  1227. { 0x125b4, 0x1 },
  1228. { 0x126b4, 0x1 },
  1229. { 0x127b4, 0x1 },
  1230. { 0x128b4, 0x1 },
  1231. { 0x13011, 0x1 },
  1232. { 0x13012, 0x1 },
  1233. { 0x13013, 0x180 },
  1234. { 0x13018, 0x1 },
  1235. { 0x13002, 0x6209 },
  1236. { 0x130b2, 0x1 },
  1237. { 0x131b4, 0x1 },
  1238. { 0x132b4, 0x1 },
  1239. { 0x133b4, 0x1 },
  1240. { 0x134b4, 0x1 },
  1241. { 0x135b4, 0x1 },
  1242. { 0x136b4, 0x1 },
  1243. { 0x137b4, 0x1 },
  1244. { 0x138b4, 0x1 },
  1245. { 0x2003a, 0x2 },
  1246. { 0xc0080, 0x2 },
  1247. { 0xd0000, 0x1 },
  1248. };
  1249. struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
  1250. {
  1251. /* P0 3200mts 1D */
  1252. .drate = 3200,
  1253. .fw_type = FW_1D_IMAGE,
  1254. .fsp_cfg = lpddr4_fsp0_cfg,
  1255. .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
  1256. },
  1257. {
  1258. /* P1 400mts 1D */
  1259. .drate = 400,
  1260. .fw_type = FW_1D_IMAGE,
  1261. .fsp_cfg = lpddr4_fsp1_cfg,
  1262. .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
  1263. },
  1264. {
  1265. /* P1 100mts 1D */
  1266. .drate = 100,
  1267. .fw_type = FW_1D_IMAGE,
  1268. .fsp_cfg = lpddr4_fsp2_cfg,
  1269. .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
  1270. },
  1271. {
  1272. /* P0 3200mts 2D */
  1273. .drate = 3200,
  1274. .fw_type = FW_2D_IMAGE,
  1275. .fsp_cfg = lpddr4_fsp0_2d_cfg,
  1276. .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
  1277. },
  1278. };
  1279. /* lpddr4 timing config params on EVK board */
  1280. struct dram_timing_info dram_timing = {
  1281. .ddrc_cfg = lpddr4_ddrc_cfg,
  1282. .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
  1283. .ddrphy_cfg = lpddr4_ddrphy_cfg,
  1284. .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
  1285. .fsp_msg = lpddr4_dram_fsp_msg,
  1286. .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
  1287. .ddrphy_pie = lpddr4_phy_pie,
  1288. .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
  1289. .fsp_table = { 3200, 400, 100, },
  1290. };