spl.c 2.3 KB

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  1. /*
  2. * Copyright 2018-2019 NXP
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <spl.h>
  8. #include <asm/io.h>
  9. #include <asm/mach-imx/iomux-v3.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx8mn_pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/arch/ddr.h>
  15. #include <dm/uclass.h>
  16. #include <dm/device.h>
  17. #include <dm/uclass-internal.h>
  18. #include <dm/device-internal.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int spl_board_boot_device(enum boot_device boot_dev_spl)
  21. {
  22. return BOOT_DEVICE_BOOTROM;
  23. }
  24. void spl_dram_init(void)
  25. {
  26. ddr_init(&dram_timing);
  27. }
  28. void spl_board_init(void)
  29. {
  30. struct udevice *dev;
  31. int ret;
  32. puts("Normal Boot\n");
  33. ret = uclass_get_device_by_name(UCLASS_CLK,
  34. "clock-controller@30380000",
  35. &dev);
  36. if (ret < 0)
  37. printf("Failed to find clock node. Check device tree\n");
  38. }
  39. #ifdef CONFIG_SPL_LOAD_FIT
  40. int board_fit_config_name_match(const char *name)
  41. {
  42. /* Just empty function now - can't decide what to choose */
  43. debug("%s: %s\n", __func__, name);
  44. return 0;
  45. }
  46. #endif
  47. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  48. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  49. static iomux_v3_cfg_t const uart_pads[] = {
  50. IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  51. IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  52. };
  53. static iomux_v3_cfg_t const wdog_pads[] = {
  54. IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  55. };
  56. int board_early_init_f(void)
  57. {
  58. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  59. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  60. set_wdog_reset(wdog);
  61. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  62. init_uart_clk(1);
  63. return 0;
  64. }
  65. void board_init_f(ulong dummy)
  66. {
  67. int ret;
  68. arch_cpu_init();
  69. init_uart_clk(1);
  70. board_early_init_f();
  71. timer_init();
  72. preloader_console_init();
  73. /* Clear the BSS. */
  74. memset(__bss_start, 0, __bss_end - __bss_start);
  75. ret = spl_init();
  76. if (ret) {
  77. debug("spl_init() failed: %d\n", ret);
  78. hang();
  79. }
  80. enable_tzc380();
  81. /* DDR initialization */
  82. spl_dram_init();
  83. board_init_r(NULL, 0);
  84. }
  85. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  86. {
  87. puts("resetting ...\n");
  88. reset_cpu(WDOG1_BASE_ADDR);
  89. return 0;
  90. }